This paper proposes high-order differential edge modulation signaling (DEMS) for high-speed wireline links. We examine the performance of DEMS and present expressions for the symbol error rate in the presence of additive wideband noise. We find that the signal-to-noise ratio and symbol error rate improve for edge modulation relative to traditional amplitude-modulated signaling. Simulations with scaled supply voltages and lossy wireline channels confirm the improved voltage and timing margins of DEMS. We present expressions for the power spectral density of DEMS to illustrate that it is more spectrally efficient than conventional baseband modulation schemes, including pulse-amplitude modulation, alternate mark inversion, and Manchester-encoded signaling.

We present an approach to characterizing and modeling spiking neurons based on the theory of the impulse sensitivity function (ISF). The ISF concept, originally developed for the design of electronic oscillators, is applied and extended to neurons. The analysis and design of synchronization, entrainment, and phase locking in neurons is accomplished using ISF theory. A circuit example of a biomimetic silicon leaky-integrate- and-fire neuron with positive feedback is presented, and the neuron's ISF is characterized. The insights gained allow the neuron's injection locking behavior, lock range, and relative phase to be predicted and optimized. Close agreement between theory and simulation is demonstrated.

We present a simple and intuitive analysis of super-regeneration that takes into account the periodically time-varying nature of a superregen operated in linear mode. We analyze the low-pass equivalent of a superregen as a starting point. Insights from this analysis guide the formal derivation of the amplifier's time-dependent impulse response, as well as of the operating conditions under which it is valid. Using the impulse response, we can easily determine the amplifier's response to arbitrary inputs as well as its frequency domain properties.

We present a quadrature-generation method that is based on parametric energy transfer to an LC resonator. The phase-sensitive nature of parametric pumping is used to generate a signal in quadrature with an incoming clock signal. The pumped LC resonator is tuned by a digital calibration loop toward the input signal frequency across the tuning range. Phase interpolation is achieved by tuning the resonator frequency away from the incoming signal frequency. Implemented in 65nm CMOS, the prototype dissipates 0.96mW and provides quadrature signals with an accuracy of 2 degrees (~1ps) over an input frequency range of 5.3-to-6.75GHz. The method is also used to achieve a phase interpolation range of 23 to 170 degrees at 6GHz.

Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Vias (TSVs) provide a promising area- and power-efficient way to support communication between different stack layers. Unfortunately, low TSV yield significantly impacts design of three-dimensional die stacks with a large number of TSVs. This paper presents a defect-tolerance technique for TSVs-based multi-bit links through an efficient and effective use of redundancy. This technique is ideally suited for three-dimensional network-on-chip (NoC) links. Simulation results demonstrate significant yield improvement, from 66% to 98%, with a low area cost (17% on a vertical link in a NoC switch, which leads a modest 2.1% increase the total switch area) in 130 nm technology, with minimal impact of VLSI design and test flows.

Experimental verification of noise models is one of the major challenges in noise modeling. A circuit-based noise characterization technique is introduced which uses phase noise measurement data to extract MOSFET noise parameters. After a brief discussion on MOSFET noise, experimental data is presented on the severity of excess noise in a 0.18μm CMOS process using the proposed technique. It is shown that in this process, the noise power of minimum-channel-length devices is up to 6 dB larger than that of long-channel devices. The proposed technique can be used for model verification as well as for parameter extraction in developing CMOS processes.

Reams of data pertaining directly to the core health services research mission are accumulating in large-scale organizational and clinical information systems. Health services researchers who grasp the structure of information systems and databases and the function of software applications can use existing data more effectively, assist in establishing new databases, and develop new tools to survey populations and collect data. At the same time, informaticians are needed who can structure databases that serve the needs of health service research and who can design and evaluate applications that effectively improve health care delivery. As long as health services researchers and informaticians work in separate spheres, however, opportunities to use data from health care encounters to improve care, expand knowledge, and develop more effective policies will be missed. This paper provides a brief exploration of 1) existing successful collaborations between health services researchers and informaticians and 2) needs and opportunities for additional joint work in several core research areas.

OBJECTIVE: Problems involving drug knowledge are one of the most common causes of serious medication errors. Although the information that clinicians need is often available somewhere, retrieving it expeditiously has been problematic. At the same time, clinicians are faced with an ever-expanding pharmacology knowledge base. Recently, point-of-care technology has become more widely available and more practical with the advent of handheld, or palmtop, computing. Therefore, the authors evaluated the clinical contribution of a drug database developed for the handheld computer. ePocrates Rx (formerly known as qRx; ePocrates, San Carlos, California) is a comprehensive drug information guide that is downloadable free from the Internet and designed for the Palm OS platform align="right". DESIGN: A seven-day online survey of 3,000 randomly selected ePocrates Rx users was conducted during March 2000. MEASUREMENTS: User technology experience, product evaluation and usage patterns, and the effects of the drug reference database on information-seeking behavior, practice efficiency, decision making, and patient care. RESULTS: The survey response rate was 32 percent (n=946). Physicians reported that ePocrates Rx saves time during information retrieval, is easily incorporated into their usual workflow, and improves drug-related decision making. They also felt that it reduced the rate of preventable adverse drug events. CONCLUSIONS: Self-reported perceptions by responding clinicians endorse improved access to drug information and improved practice efficiency associated with the use of handheld devices. The clinical and practical value of using these devices in clinical settings will clearly grow further as wireless communication becomes more ubiquitous and as more applications become available.

We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

A strong demand for wireless products, an insatiable thirst for spectrum that pushes carrier frequencies ever upward, and the constant quest for higher performance at lower power and cost, have recently driven the development of radio frequency integrated circuit (RFIC) technology in unprecedented ways. These pressures are stimulating novel solutions that allow RFICs to enjoy more of the benefits of Moore's law than has been the case in the past. In addition to regular raw transistor speed increases, the growing number of interconnect layers allows the realization of improved inductors, capacitors, and transmission lines. A deeper understanding of noise at both the device and circuit level has improved the performance of low noise amplifiers (LNAs) and oscillators. Finally, an appropriate raiding of circuit ideas dating back to the vacuum tube era enables excellent performance, even when working close to the limits of a technology. This paper surveys some of these developments in the context of low-power RF CMOS technology, with a focus on an illustrative implementation of a low-power 5-GHz wireless LAN receiver in 0.25-/spl mu/m CMOS. Thanks to these recent advances in passive components and active circuits, the blocks comprising the receiver consume a total of approximately 37 mW. These blocks include an image-reject LNA, image-reject downconverter, and a complete frequency synthesizer. The overall noise figure is 5 dB, and the input-referred third-order intercept (IIP3) is -2 dBm. To underscore that 5 GHz does not represent an upper bound by any means, this paper concludes with a look at active circuits that function beyond 15-20 GHz, and a characterization of on-chip transmission lines up to 50 GHz, all in the context of how scaling is expected to shape future developments.

We present an efficient method for optimal design and synthesis of CMOS inductors for use in RF circuits.This method uses the the physical dimensions of the inductor as the design parameters and handles a variety of specifications including fixed value of inductance, minimum self-resonant frequency, minimum quality factor, etc. Geometric constraints that can be handled include maximum and minimum values for every design parameter and a limit on total area.Our method is based on formulating the design problem as a special type of optimization problem called geometric programming, for which powerful efficient interior-point methods have recently been developed.This allows us to solve the inductor synthesis problem globally and extremely efficiently.Also, we can rapidly compute globally optimal trade-off curves between competing objectives such as quality factor and total inductor area.We have fabricated a number of inductors designed by the method, and found good agreement between the experimental data and the specifications predicted by our method.

Presents a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular, the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal trade-off curves between competing objectives such as phase noise and power.

Article Free Access Share on GPCAD: a tool for CMOS op-amp synthesis Authors: Maria del Mar Hershenson Electrical Engineering Department, Stanford University, Stanford CA Electrical Engineering Department, Stanford University, Stanford CAView Profile , Stephen P. Boyd Electrical Engineering Department, Stanford University, Stanford CA Electrical Engineering Department, Stanford University, Stanford CAView Profile , Thomas H. Lee Electrical Engineering Department, Stanford University, Stanford CA Electrical Engineering Department, Stanford University, Stanford CAView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 296–303https://doi.org/10.1145/288548.288628Online:01 November 1998Publication History 45citation513DownloadsMetricsTotal Citations45Total Downloads513Last 12 Months41Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A 1.4-GHz LC voltage-controlled oscillator has been implemented in a MOSIS 0.5-µm CMOS process. Complementary cross-coupled PMOS and NMOS transistors enhance single-ended symmetry at each of the resonant nodes, reducing close-in phase noise. Tapped bond wires provide a resonant tank with high Q. At an offset frequency of 100 kHz, the measured phase noise is -107 dBc/Hz with 3 mW power dissipation from a 3.0 V supply. NMOS gate capacitors achieve a 17% tuning range.

A new phase noise model was used to optimize a differential ring VCO for minimum power consumption. We compare the phase noise performance of three buffer stages using clamped, symmetric and cross-coupled loads, respectively. We propose a cross-coupled buffer topology that achieves lower phase noise by exploiting symmetry. Measured phase noise for a 1.2mW, 150MHz VCO fabricated in 0.5µm CMOS is -103.9dBc/Hz at 500KHz offset, showing good agreement with the theory.