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Fred J. Pollack

dblp:92/4303 · DBLP profile ↗
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8ranked-venue papers
3as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 5 · 2 first-authorSystems, architecture and hardware · 3 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
7 papers
Processor architecture and microarchitecture · 44% Integrated circuit design · 29% Hardware reliability and fault tolerance · 9%
Software engineering, system software, and programming languages
6 papers
Operating systems · 90% Programming languages and type systems · 10%

Topics — the 21 heaviest of 26, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
microprocessor design
0.012001
Coming challenges in microarchitecture and architecture · Proc. IEEE 2001
Integrated circuit design › semiconductor device fabrication
CMOS technology
0.011999
New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies · MICRO 1999
Hardware reliability and fault tolerance
soft errors
0.012001
Coming challenges in microarchitecture and architecture · Proc. IEEE 2001
Integrated circuit design
technology scaling
0.011999
New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies · MICRO 1999
Operating systems
interprocess communication
0.021983
Interprocess Communication and Processor Dispatching on the Intel 432 · ACM Trans. Comput. Syst. 1983
A Unified Model and Implementation for Interprocess Communication in a Multiprocessor Environment · SOSP 1981
Processor architecture and microarchitecture
capability-based architecture
0.011982
Supporting Ada Memory Management in the iAPX-432 · ASPLOS 1982
Memory systems › memory management
virtual memory
0.011982
Supporting Ada Memory Management in the iAPX-432 · ASPLOS 1982
Operating systems › multiprocessing
multiprocessor operating system
0.011981
iMAX: A Multiprocessor Operating System for an Object-Based Computer · SOSP 1981
Operating systems › resource management › storage management
persistent object stores
0.011981
The iMAX-432 Object Filing System · SOSP 1981
Storage systems
file systems
0.011981
The iMAX-432 Object Filing System · SOSP 1981
Storage systems
storage reliability
0.011981
The iMAX-432 Object Filing System · SOSP 1981
Operating systems › kernel
kernel design
0.011975
Policy/Mechanism Separation in HYDRA · SOSP 1975
Operating systems › kernel › kernel design
microkernel
0.011975
Policy/Mechanism Separation in HYDRA · SOSP 1975
Operating systems › operating system design
policy-mechanism separation
0.011975
Policy/Mechanism Separation in HYDRA · SOSP 1975
Parallel and multicore computing › parallel programming models
message passing
0.011983
Interprocess Communication and Processor Dispatching on the Intel 432 · ACM Trans. Comput. Syst. 1983
Programming languages and type systems
abstract data types
0.011981
iMAX: A Multiprocessor Operating System for an Object-Based Computer · SOSP 1981
Processor architecture and microarchitecture › instruction set architecture
capability-based addressing
0.011981
The iMAX-432 Object Filing System · SOSP 1981
Operating systems › resource management › process management
CPU scheduling
0.011975
Policy/Mechanism Separation in HYDRA · SOSP 1975
Operating systems › resource management
memory management
0.011975
Policy/Mechanism Separation in HYDRA · SOSP 1975
Operating systems › resource management › memory management › virtual memory
paging
0.011975
Policy/Mechanism Separation in HYDRA · SOSP 1975
Operating systems
resource management
0.011975
Policy/Mechanism Separation in HYDRA · SOSP 1975

Methods — techniques the papers use, named apart from their topics

technology scaling analysis · 0.0queuing · 0.0binding · 0.0architectural case study · 0.0
YearPublicationVenuePosition
2001 Coming challenges in microarchitecture and architecture
abstract
In the past several decades, the world of computers and especially that of microprocessors has witnessed phenomenal advances. Computers have exhibited ever-increasing performance and decreasing costs, making them more affordable and in turn, accelerating additional software and hardware development that fueled this process even more. The technology that enabled this exponential growth is a combination of advancements in process technology, microarchitecture, architecture, and design and development tools. While the pace of this progress has been quite impressive over the last two decades, it has become harder and harder to keep up this pace. New process technology requires more expensive megafabs and new performance levels require larger die, higher power consumption, and enormous design and validation effort. Furthermore, as CMOS technology continues to advance, microprocessor design is exposed to a new set of challenges. In the near future, microarchitecture has to consider and explicitly manage the limits of semiconductor technology, such as wire delays, power dissipation, and soft errors. In this paper we describe the role of microarchitecture in the computer world present the challenges ahead of us, and highlight areas where microarchitecture can help address these challenges.
Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen
Proc. IEEE5
1999 New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies
Fred J. Pollack
MICRO1
1983 Interprocess Communication and Processor Dispatching on the Intel 432
abstract
A unified facility for interprocess communication and processor dispatching on the Intel 432 is described.The facility is based on a queuing and binding mechanism called a port.The goals and motivations for ports, both abstract and implementation views of them, and their absolute and comparative performance are described.
George W. Cox, William M. Corwin, Konrad Lai, Fred J. Pollack
ACM Trans. Comput. Syst.4
1982 Supporting Ada Memory Management in the iAPX-432
abstract
In this paper, we describe how the memory management mechanisms of the Intel iAPX-432 are used to implement the visibility rules of Ada. At any point in the execution of an Ada® program on the 432, the program has a protected address space that corresponds exactly to the program's accessibility at the corresponding point in the program's source. This close match of architecture and language did not occur because the 432 was designed to execute Ada—it was not. Rather, both Ada and the 432 are the result of very similar design goals.To illustrate this point, we compare, in their support for Ada, the memory management mechanisms of the 432 to those of traditional computers. The most notable differences occur in heap-space management and multitasking. With respect to the former, we describe a degree of hardware/software cooperation that is not typical of other systems. In the latter area, we show how Ada's view of sharing is the same as the 432, but differs totally from the sharing permitted by traditional systems. A description of these differences provide some insight into the problems of implementing an Ada compiler for a traditional architecture.
Fred J. Pollack, George W. Cox, Dan W. Hammerstrom, Kevin C. Kahn, Konrad Lai, Justin R. Rattner
ASPLOS1
1981 A Unified Model and Implementation for Interprocess Communication in a Multiprocessor Environment
abstract
This paper describes interprocess communication and process dispatching on the Intel 432. The primary assets of the facility are its generality and its usefulness in a wide range of applications. The conceptual model, supporting mechanisms, available interfaces, current implementations, and absolute and comparative performance are described.
George W. Cox, William M. Corwin, Konrad Lai, Fred J. Pollack
SOSP4
1981 iMAX: A Multiprocessor Operating System for an Object-Based Computer
abstract
The Intel iAPX 432 is an object-based microcomputer which, together with its operating system iMAX, provides a multiprocessor computer system designed around the ideas of data abstraction. iMAX is implemented in Ada and provides, through its interface and facilities, an Ada view of the 432 system. Of paramount concern in this system is the uniformity of approach among the architecture, the operating system, and the language. Some interesting aspects of both the external and internal views of iMAX are discussed to illustrate this uniform approach.
Kevin C. Kahn, William M. Corwin, T. Don Dennis, Herman D'Hooge, David E. Hubka, Linda A. Hutchins, John T. Montague, Fred J. Pollack
SOSP8
1981 The iMAX-432 Object Filing System
abstract
iMAX is the operating system for Intel's iAPX-432 computer system. The iAPX-4321 is an object-oriented multiprocessor architecture that supports capability-based addressing. The object filing system is that part of iMAX that implements a permanent reliable object store.
Fred J. Pollack, Kevin C. Kahn, Roy M. Wilkinson
SOSP1
1975 Policy/Mechanism Separation in HYDRA
abstract
The extent to which resource allocation policies are entrusted to user-level software determines in large part the degree of flexibility present in an operating system. In Hydra the determination to separate mechanism and policy is established as a basic design principle and is implemented by the construction of a kernel composed (almost) entirely of mechanisms. This paper presents three such mechanisms (scheduling, paging, protection) and examines how external policies which manipulate them may be constructed. It is shown that the policy decisions which remain embedded in the kernel exist for the sole purpose of arbitrating conflicting requests for physical resources, and then only to the extent of guaranteeing fairness.
Roy Levin, Ellis S. Cohen, William M. Corwin, Fred J. Pollack, William A. Wulf
SOSP4