Article Frequency domain microwave modeling using retarded partial element equivalent circuits Share on Authors: Hansruedi Heeb View Profile , Saila Ponnapalli View Profile , Albert E. Ruehli View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 702–706https://doi.org/10.1145/157485.165097Published:01 July 1993 3citation234DownloadsMetricsTotal Citations3Total Downloads234Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

With ever increasing clock frequencies, accurate 3-D interconnect analysis in chips and packages is becoming a necessity. The retarded partial element equivalent circuit (rPEEC) method has been successfully applied to 3-D analysis but for large problems it becomes expensive in CPU and memory usage, and in time domain it sometimes has numerical problems. Complex frequency hopping (CFH), a new multi-point moment-matching technique, is expanded to handle retarded networks. CFH speeds up rPEEC frequency domain analysis of large frequency bands significantly. It also allows the efficient calculation of resonances and - most importantly - enables time domain modeling of rPEEC networks that have so far resisted analysis by any other method.

A general approach for modeling 3-D layout geometries is presented. In particular, the partial-element equivalent circuit (PEEC) technique has been used successfully to model interconnect structures for chips and packages. The technique, which is circuit based, permits the electrical modeling of arbitrary 3-D geometries and allows 3-D transmission line properties to be analyzed. Recently, the technique has been extended to include retardation and dielectric layers. The authors have experimented with the use of the asymptotic waveform evaluation (AWE) approach to speed up the solution of the resulting circuit equations.>

It is shown that retardation effects, due to the finite speed of electromagnetic interactions, play a significant role for PC-board interconnects. It is demonstrated that in some cases errors of more than an order of magnitude result in some frequency components when retardation is neglected. Extensions to a circuit simulator are introduced that make it possible to do retarded circuit simulation. Specifically, an algorithm to extend SPICE-level simulators to include retardation is presented. Comparisons with analytical equations, the method of moments, and with measurements show good agreement.>

A realistic approach is introduced for the computation of the electromagnetic radiation interference (EMI) from printed circuit boards. The approach is suitable for large problems and real circuit boards can be investigated. Each trace and its source and loads are represented as electrical circuits and a conventional time-domain circuit simulation is used to find the currents. The field is then calculated by applying the free-space Green's function to all currents including the polarization currents. This is, to the authors' knowledge, the first CAD tool which can predict EMI from basic principles.>

The time-domain modeling of the connections in a high-speed computer is such of a complexity that practical problems can only be solved using suitable approximations. Presented are the results of a time-domain modeling work where a novel and faster representation of the capacitances has been developed. Instead of a circuit with O(n/sup 2/) capacitances (where n is the number of conductors), an equivalent circuit of n pseudo-capacitances and n dependent voltage sources is used. Due to the increased sparsity of the simulation matrix, the method considerably speeds up the SPICE or ASTAP compute time. In addition, pseudo-capacitances and voltage sources can be calculated from the coefficient of potential matrix, thus making the calculation of the capacitance matrix unnecessary. This reduces the computational complexity of the capacitance extraction O(n/sup 3/) to O(n/sup 2/) resulting in another major speed-up.>