This paper presents a new approach to detect weak signatures of fault frequency components associated with inner race bearing faults in low voltage, high current Permanent Magnet Synchronous Motor (PMSM) under light load conditions. Inner race faults in bearing produce very weak signatures in the stator current spectrum, which is difficult to detect due to the high amplitude fundamental component of motor current. The proposed method combines a preconditioning Extended Kalman Filter (EKF), Low-Rank Approximation of Hankel Matrix, and the Matrix Pencil Method (MPM) to achieve robust fault detection by suppressing the high magnitude fundamental component. The EKF is utilized to pre-process the current signal, reducing noise and extracting fault-related information. A subsequent Low-Rank Approximation generates a Hankel matrix, capturing the fault-related damped sinusoidal components in the presence of background noise. The MPM is then employed to estimate the fault-related frequency components. Experimental evaluations are conducted on synthetic and real-world data to assess the performance of the proposed method. Results indicate improved accuracy in estimating the fault frequency components, even in the presence of noise and other disturbances. Fault detection capability is significantly enhanced, demonstrating the effectiveness of the proposed approach. This work contributes to a comprehensive fault detection framework for PMSM motors, enabling early identification of inner race faults. The proposed method shows promise for practical implementation in industrial applications, facilitating timely maintenance and reducing the risk of catastrophic failures.

Charge equalization is essential to maximizing the performance and functionality of lithium-ion battery packs. Various equalization topologies have been developed using charge equalization circuits (CEC) integrated within the Battery Man-agement System (BMS). However, when implemented using buck-boost CEC with conventional switching operations, the adjacent cell-to-cell ($AC2C$) topology exhibits the maximum equalization loss. Therefore, a maximum-minimum equalization algorithm is proposed to control the cell current by regulating the control input of the CEC, which will improve the efficiency of the equalization operation. In this work, two types of CECs, namely buck-boost and dual half-bridge, have been investigated for the series AC2C equalization topology, and a comparison study between CECs in terms of per-unit development cost, equalization efficiency, and time for different control approaches has been pre-sented. The detailed mathematical modeling for each CEC type is formulated to replicate the identical equalization operation. The proposed methodology is validated with$a$48 V, 20 Ah battery pack developed in the PLECS simulation environment.

Current research on energy related problems such as eco-routing, eco-driving and range prediction for electric vehicles (EVs) primarily considers the effect of longitudinal dynamics on EV energy consumption. However, real-world driving includes longitudinal as well as lateral motion. Therefore, it is important to understand the effects of lateral dynamics on battery energy consumption. This paper conducts an analysis of the stated effect and validates its significance through simulations. Specifically, this study demonstrates that inclusion of the effect of lateral dynamics can improve accuracy and reliability of solutions in eco-routing, eco-driving and range prediction applications.

Surface wave tomography is performed by first estimating surface wave dispersion curves and then inverting them. The objective of this paper is the efficient and reliable estimation of the group velocity dispersion curves of surface waves. In this paper, group velocity dispersion curves of surface waves recorded at a single station with known location of seismic source or between a pair of stations are estimated using continuous wavelet transform (CWT). The advantage of CWT is its multi-resolution property and flexible choice of analyzing function. In the proposed method, the number of CWT filters used are almost half of the total number of filters used in the conventional frequency-time analysis (FTAN) method. The CWT coefficients of the seismogram are the functions of time and scale (analogues to wave period). The arrival time to reach the peak of the envelope function of CWT coefficients is estimated to calculate group velocity of the surface waves. Group velocity dispersion curve of the surface waves is the plot of change of group velocity with the period. Synthetic test data and ambient noise recordings of MesoAmerica Seismic Experiment (MASE) stations are acquired to investigate the performance of the proposed method. It is observed that the proposed method effectively retrieves the weaker surface waves and results the broader band group-velocity dispersion curve when compared to the conventional FTAN method. The proposed method is also found to be computationally efficient.

This paper presents a technique to study and estimate the dc performance of lateral power MOSFET switches used in on-chip dc-dc converters. The dc performance is characterized by the on-resistance and current distribution profile in the switch layout. In the proposed approach, a netlist is generated that consists of the parasitic resistances extracted from the metal interconnects along with the MOS device fingers present in the layout. This approach is modular and exploits repetitive patterns of power MOSFET layouts to expedite the extraction process. The extracted resistance values are computed from the geometrical and technological parameters of the metal polygons without the requirement of solving complex electromagnetic (EM) field equations. Comparison of results with an industry standard EM solver tool as well as experimental measurements amply demonstrates the computational efficiency and accuracy of the approach.

The verification community anticipates the adoption of assertions in the Analog and Mixed-Signal (AMS) domain in the near future. Several questions need to be answered before AMS assertions are brought into practice, such as: (a) How will the languages for AMS assertions be different from the ones in the digital domain? (b) Does the analog simulator have to be assertion aware? (c) If so, then how and where on the time line will the AMS assertion checker synchronize with the analog simulator? and (d) What will be the performance penalty for monitoring AMS assertions accurately over analog simulation? This article attempts to answer these questions through theoretical analysis and empirical results obtained from industrial test cases. We study logics which extend Linear Temporal Logic (LTL) with predicates over real variables, and show that further extensions allowing the binding of real-valued variables across time makes the logic undecidable. We present a toolkit which can integrate with existing AMS simulators for checking AMS assertions on practical designs. We study the problem of synchronizing the AMS simulator with the AMS assertion checker and demonstrate the performance penalty of different synchronization options.

As research on developing assertion languages for the analog and mixed-signal (AMS) domain gains in momentum, it is increasingly being felt that extensions of existing assertion languages like property specification language and SystemVerilog assertions into the AMS domain are not adequate for expressing the analog design intent. This is largely due to the intricacy of the analog behavioral intent which cannot be captured purely in terms of logic. In this paper, we show that by using auxiliary forms of formal specifications such as abstract state machines and real-valued functions, called auxiliary functions, as references for AMS assertions, it becomes possible to model complex AMS behavioral properties. In addition, we present complexity results for the satisfiability problem of such specifications. This approach leverages the growing adoption of AMS behavioral modeling in the industry. This paper also shows that the use of auxiliary state machines allows us to separate out the scope of different analog assertions leading to significant performance gains in the assertion checking overhead.

Power Management Units (PMUs) are large integrated circuits consisting of many predesigned mixed-signal components. PMU integration poses a serious verification problem considering the size of the integrated circuit and the complexity of analog simulation. In this article we present an approach for automatic generation of behavioral models for PMU components from top-down skeleton models, fitted with parameter values estimated by bottom-up parameter extraction algorithms. It is shown that replacing PMU components with these autogenerated hybrid automata-based abstract behavioral models enables significant simulation speedup (> 20X on our industrial test cases) and helps in early detection of integration errors. The article also justifies the level of accuracy in our models with respect to the goal of verifying integrated PMUs. The approach presented in this work is implemented in the form of a tool suite called Chassis.

Prototyping on FPGA has become a main stream verification methodology for hardware design, test development, software co-design etc. in the area of digital VLSI. In the case of test development, FPGA serves as a virtual DUT (Design under Test) and test patters are applied from automatic test equipment (ATE). This verifies not only the chip with design for test (DFT) circuitry and test program but also the entire test setup involving virtual DUT, load board, interconnections with ATE etc. Although, FPGA based platform is used widely for test program verification of digital ICs, this technique is not used for analog/mixed signal (AMS) circuits because of the difficulty in implementing AMS circuits in FPFAs. This work is concerned with the development of a test emulation platform, termed as hand-in-hand test flow, of AMS circuits based on FPGA. The proposed methodology exploits fixed-point modeling and DSP implementation technique facilitated by latest FPGAs to model the AMS circuits. The proposed hand-in-hand test flow for AMS circuits will help the test engineers to start their test plan concurrently with the design engineers and validate them much prior to the first silicon. We have illustrated the proposed scheme using the case study of an analog phase locked loop (PLL) on Xilinx® Virtex"-4 FPGA. The FPGA emulation results show that performance of the emulated analog PLL (e.g., acquisition characteristics, step response) matches well with that of behavioral simulation.

This paper presents the extensions and experimental validations of a new approach recently developed by the authors for accurate estimation of on-resistance (RDS(on)) of large lateral power MOSFET switch layouts present in on-chip DC-DC converters. This approach exploits the highly symmetric and repetitive patterns of power MOSFET layouts to generate the extracted resistance netlist efficiently resulting significant speed up in resistance extraction process. The extracted resistance values in the interconnects are computed from the metal geometry using models that relate resistance values to the geometric parameters of the layout. Comparison of results with an industry standard EM solver tool as well as experimental measurements for power MOSFET layouts of W/L ratio 105amply demonstrate the computational efficiency and accuracy of the approach establishing its applicability for industrial on-chip power array implementations.

Standard wireless communication circuits extensively use bandpass Gm-C filters, whose Total Harmonic Distortion (THD) and Intermodulation Distortion (IMD) have been estimated and modeled previously. However previous approaches have considered only third order nonlinearity effects assuming fully balanced OTAs. This assumption does not hold good for practical circuits. Hence a structural modeling approach which takes into consideration all perceptible orders of nonlinearity has been proposed. The proposed approach abstracts the nonlinear elements from the Gm-C filter and models them using a macro-modeling technique. Results from the proposed model are found to be in good agreement with a designed weakly nonlinear Gm-C filter with a 4 times improvement in simulation time. Extension of the approach to the case of a lossy integrator shows improved accuracy over existing modeling approaches.

This work is concerned with the development of generic, non-intrusive and flexible algorithms for the design of digital circuits with on line testing (OLT) capability. Most of the works presented in the literature on OLT have used single stuck at fault models. However, in deep submicron era single s-a fault models may not capture more than a fraction of the real defects. To cater to the problem it is now advocated that additional fault models such as Bridging faults, Transition faults, Delay faults etc. are also used. The proposed technique is one of the first works that enables on-line detection of bridging faults and provides a high value of n for the n-Detect tests. The technique can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The results illustrate that with marginal increase in area overhead, if compared to ones with single s-a fault coverage, the proposed scheme also provides coverage for bridging faults and high value of n for n-Detect coverage.

This work is concerned with the development of algorithms and CAD tools for the design of digital circuits with on line monitoring capability. An existing theory of fault detection and diagnosis available in the literature on discrete event systems has been adopted for on-line detection of stuck-at faults in digital circuits. Efficient computational techniques to deal with very large state spaces based on ordered binary decision diagrams and abstraction have been proposed. Based on these a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capability without the requirement of any modification to the core and can handle generic digital circuits with cell count as high as 15,000 and having the order of 2/sup 500/ states. Chips, designed using this methodology have been fabricated in 0.18-micron technology and are tested to be working.

In the area of Discrete Event Systems (DES) a growing need is being felt for new classes of models to describe both logical and timed behaviors efficiently. Among the frameworks presented recently, the Finitely Recursive Process model is a powerful one. However it is solely based on a characterization of the event strings generated in the DES. In this work an augmented version of the above model is presented, where the notion of a collection of system related variables, forming the ‘state-space’ of the system, is introduced. A concept of a ‘silent transition’ is introduced for effective modelling of concurrent DES. To allow nonuniqueness of the initial state, an extended process framework is presented and a recursive characterization is made in terms of a collection of constant processes and process operators. A general Timed Transition Model (Ostroff, 1990) is modelled as an extended process to show the describing power of the framework. A model of a robot controller is presented to show the usefulness of its different features in modelling real systems.