We present a practical flow that automates the process of analyzing noise failures and determining and implementing the most appropriate design fixes in high performance designs. For each noise problem, the flow implicitly identifies the most sensitive relevant electrical parameter(s) which it then maps to a physical solution that minimizes design perturbation. Integrated with standard physical synthesis, it was used extensively in a high volume 90 nm multi-GHz microprocessor project.

Block-processing can decrease the time and power required to perform any given computation by simultaneously processing multiple samples of input data. The effectiveness of block-processing can be severely limited, however, if the delays in the dataflow graph of the computation are placed suboptimally. In this paper we investigate the application of retiming for improving the effectiveness of block-processing in computations. In particular, we consider the k-delay problem : Given a computation dataflow graph and a positive integer k , we wish to compute a retimed computation graph in which the original delays have been relocated so that k data samples can be processed simultaneously and fully regularly. We give an exact integer linear programming formulation for the k -delay problem. We also describe an algorithm that solves the k -delay problem fast in practice by relying on a set of necessary conditions to prune the search space. Experimental results with synthetic and random benchmarks demonstrate the performance improvements achievable by block-processing and the efficiency of our algorithm.

The retiming transformation can be used to optimize synchronous circuits for maximum speed of operation by relocating their storage elements. For relatively simple delay models, an optimal retiming of a given circuit can be computed in polynomial time. Under more comprehensive delay models, however, the retiming problem is solved by resorting to branch-and-bound techniques. In this paper, we investigate retiming under delay models that encompass load-dependent gate delays, register delays, interconnect delays, and clock skew. For the most general of our delay models, we express the retiming problem as a set of integer linear programming (ILP) constraints that can be solved using ILP techniques. For less general delay models, which encompass circuits with monotonic clock skews and load-dependent gate delays, we give an integer monotonic programming formulation for the retiming problem and an asymptotically efficient retiming algorithm. Our algorithm re-times any given edge-triggered circuit to achieve a specified clock period in O(V/sup 3/ F) steps, where V is the number of combinational logic gates in the circuit and F is a constant no greater than the circuit's register count. We have implemented our algorithms in DELAY, a software tool for optimizing synchronous circuits, and have evaluated their performance on benchmark circuits.

Abstract|Block-processing is a powerful and popular technique for increasing computation speed by simultaneously processing several samples of data.The eectiveness of block-processing is often reduced, however, due to suboptimal placement of delays in the data ow graph of a computation.In this paper we i n v estigate an application of the retiming transformation for improving the effectiveness of block-processing in computation structures.Speci cally, w e consider the k-delay problem in which w e wish to retime any given computation so that given an integer k the resulting computation can process k data samples simultaneously in a fully regular manner.Our main contribution is an O(V 3 E+V 4 log V )-time algorithm for the k-delay problem, where V is the number of computation blocks and E is the number of interconnections in the computation.

In this paper we introduce fixed-phase retiming, an optimization technique for reducing the power dissipation of digital circuits without sacrificing their performance. In fixed-phase retiming, we first transform any given edge-triggered circuit into a two-phase level-clocked circuit by replacing each flip-flop by two level-sensitive latches. Subsequently, while keeping the latches clocked on one of the phases fixed, we relocate the remaining latches onto interconnections with high glitching activity and capacitive load. We formulate fixed-phase retiming as a Boolean monotonic linear program and give an O(V/sup 6/ log V)-time algorithm for solving it, where V is the number of combinational blocks in the circuit.

Article DELAY: an efficient tool for retiming with realistic delay modeling Share on Authors: Kumar N. Lalgudi Department of Electrical Engineering, Yale University, New Haven, CT Department of Electrical Engineering, Yale University, New Haven, CTView Profile , Marios C. Papaefthymiou Department of Electrical Engineering, Yale University, New Haven, CT Department of Electrical Engineering, Yale University, New Haven, CTView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 304–309https://doi.org/10.1145/217474.217546Online:01 January 1995Publication History 35citation265DownloadsMetricsTotal Citations35Total Downloads265Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access