In the field of very large-scale integration (VLSI) chip design, chip floorplanning plays a crucial role as it directly influences key optimization objectives such as placement wirelength. This, in turn, affects signal delay, power efficiency, routability, and overall cost. However, traditional reinforcement learning (RL) methods for chip floorplanning often oversimplify this complex and dynamic task. They tend to overlook the cascading effects of module placements and fail to fully comprehend the intricate interdependencies that are vital for making informed decisions. To address these challenges, we introduce an innovative approach that combines hypergraph graph convolutional networks (HyperGCNs) with deep recurrent Q-networks (DRQNs). This integration allows us to capture the nuanced dynamics and interconnected aspects of chip design more effectively. We enhance the traditional Markov decision process (MDP) model by incorporating a state characterization layer based on long short-term memory (LSTM) technology. Initially, HyperGCN efficiently encodes netlist information, simplifying complex graph structures into lower dimensional vectors, thereby enhancing knowledge processing. Subsequently, we treat the chip as an agent and apply the DRQN algorithm to optimize the module layout. DRQN’s LSTM utilizes a recurrent layer structure to grasp dependencies between modules, combined with the deep Q-network (DQN)’s optimization capabilities, enabling us to navigate the complexities of floorplanning. Our approach improves the state representation by encompassing a broader understanding of interconnected module characteristics. This allows our agents to make decisions that take into account the collective impact of module adjustments, rather than viewing each change in isolation. This comprehensive state representation, which includes diverse features and their evolving relationships, significantly enhances the decision-making capabilities of our agents. Our extensive experiments demonstrate that our method outperforms traditional heuristic-based and other learning-based floorplanning techniques. To the best of our knowledge, this is the first application of LSTM with DQN in circuit design, representing a significant advancement in the field.

In the realm of very large-scale integration (VLSI) chip design, chip floorplanning is essential, directly impacting key optimization objectives like placement wirelength, which in turn affects signal delay, power efficiency, routability, and overall cost. Traditional reinforcement learning (RL) methods for chip floorplanning often oversimplify the complex, dynamic nature of this task, typically overlooking the cascading effects of module placements and failing to fully grasp the intricate interdependencies crucial for informed decision-making. To address these challenges, we introduce an innovative approach that fuses hypergraph graph convolutional networks (HyperGCN) with deep Transformer Q-networks (DTQN). This integration captures the nuanced dynamics and interconnected aspects of chip design more effectively. We enhance the traditional Markov decision process (MDP) model with a state characterization layer based on Transformer technology. Initially, HyperGCN effectively encodes netlist information, simplifying complex graph structures into lower-dimensional vectors, thus enhancing knowledge processing. Subsequently, viewing the chip as an agent, we apply the DTQN algorithm to optimize the module layout. DTQN's Transformer encoder utilizes a multi-head self-attention (MSA) mechanism to grasp long-range dependencies between modules, coupled with DQN's optimization capabilities, to navigate the complexities of floorplanning. Our approach enhances the state representation by incorporating a broader understanding of the interconnected module characteristics, which allows agents to make decisions that account for the collective impact of module adjustments, rather than viewing each change in isolation. This comprehensive state representation, encompassing diverse features and their evolving relationships, significantly enhances the agent's decision-making capabilities. Our extensive experiments demonstrate that our method outperforms traditional heuristic-based and other learning-based floorplanning techniques. To our knowledge, this is the first application of the Transformer in circuit design, marking a significant advancement in the field.

For urban growth modeling, assessment metrics derived from cell-by-cell comparisons are mainly related to the size of the study area and the urban growth rate. Non-urban areas always occupy an important part of the city to which cellular automata (CA) models do not contribute much, so the simulation accuracy is often exaggerated when this part is included. To enable comparing simulation results across models, regions, and time, we developed an improved equivalent area-based assessment (EQASS) method using cell-by-cell comparison metrics. As against existing assessment methods, EQASS is computed by including the same area of urban and suburban areas (i.e., equivalent areas). EQASS was tested in three Chinese coastal cities using a heuristic CA model and two spatial statistical CA models to simulate urban growth. The results show that EQASS can exclude correct rejections that are not attributable to CA models; these correct rejections have a significant impact on the model assessment. The improved assessment can better evaluate the performance of CA models across regions and over time than the conventional assessment method that accounts for the full study area. This study extends the simulation assessment method and provides a good solution for selecting the best CA model from many candidate models.

High temperature or temperature nonuniformity has been considered as one of the most challenging problems in three-dimensional integrated circuits (3-D ICs). There have been many studies on the thermal issues in 3-D ICs floorplanning. However, most handcrafted heuristic algorithms require long iteration cycles, resulting in inefficient thermal management with no guarantee of good performance. Meanwhile, as modern integrated circuit design becomes increasingly complex, current floorplannings suffer from the “curse of dimensionality” and cannot optimize large-scale cases. Therefore, a novel thermal-aware fixed-outline 3-D IC floorplanning is proposed in this article. Since the temperature in a 3-D IC is mainly determined by a power distribution across tiers, this article proposes a deep${k}$-means clustering algorithm to cluster the modules and find a better cross-tier power distribution. This is an unsupervised machine-learning algorithm that can successfully cluster high-dimensional sample data. Then, in the global distribution (GD) stage, we not only consider the power consumption between the groups but also apply the number and area of through silicon vias (TSVs) to the clustering and analytical method in the multilevel framework. Inspired by the fact that finding the optimal TSV positions for multiple nets in the TSV assignment (TA) stage is essentially a way to maximize the benefits of nets in a competitive environment, game theory is applied to further reduce temperature and wirelength in this stage. We prove that it is an ordinal potential game, and then converge to the Nash equilibrium by the best response strategy. Experimental results demonstrate that the proposed method shows good performance in reducing the temperature of 3-D ICs, and its running time is quite fast.

High temperature and temperature nonuniformity pose significant challenges in 3-D integrated circuits (3-D ICs). Numerous studies have explored thermal issues in 3-D IC floorplanning. However, most existing handcrafted heuristic algorithms suffer from long iteration cycles, resulting in inefficient thermal management and no guarantee of optimal performance. In addition, with the increasing complexity of modern integrated circuit design, current floorplanning techniques encounter the “curse of dimensionality” and struggle to optimize large-scale cases. To address these challenges, this article proposes a novel end-to-end learning-based approach for thermal-aware fixed-outline 3-D IC floorplanning. In the tier assignment stage, we utilize a deep${k}$-means clustering algorithm to allocate modules to different tiers, aiming to achieve an improved cross-tier power distribution. In the global distribution (GD) stage, we formulate the floorplanning problem as a Markov decision process (MDP). By combining graph convolutional networks (GCNs) with a multiagent deep reinforcement learning (MADRL) algorithm, we optimize the positions of modules and through-silicon vias (TSVs), while incorporating an attention mechanism in the centralized critic to enhance cooperation among agents. Finally, in the TSV assignment (TA) stage, we refine the TSV positions using the MADRL algorithm, further reducing wirelength and temperature in 3-D ICs. Experimental results demonstrate that our proposed approach outperforms state-of-the-art heuristic-based 3-D IC floorplanner in terms of wirelength and temperature optimization.

Three-dimensional integrated circuit (3-D IC) technology has emerged as a solution to address the limitations of 2-D ICs. One critical component of 3-D ICs is the through-silicon via (TSV), which plays a crucial role in connecting signal nets and dissipating heat. The assignment of TSVs significantly impacts the wirelength and temperature of 3-D ICs. Although several studies have focused on the TSV assignment problem, most existing heuristic algorithms suffer from long iteration cycles and lack performance guarantees. Meanwhile, these methods struggle to optimize large-scale cases due to the curse of dimensionality inherent in complex IC designs. Recently, learning-based algorithms, particularly reinforcement learning (RL), have demonstrated success in solving various combinatorial optimization problems by leveraging past experiences. In this article, we propose attention-TSV assignment (ATT-TA), a novel TSV assignment method based on a multiagent deep RL (MADRL) algorithm. The TSV assignment problem is formulated as a Markov decision process (MDP), where each TSV layer serves as an independent agent. To enhance collaboration, we incorporate an attention mechanism that models and utilizes teammate strategies within a cooperative multiagent system. By applying multiagent systems, we mitigate the curse of dimensionality, while the attention mechanism enables adaptive modeling of joint strategies among agents. Notably, this is the first attempt to solve the TSV assignment problem using a MADRL algorithm. The experimental results demonstrate that compared with the state-of-the-art heuristic-based TSV assignment methods, the proposed ATT-TA approach consistently outperforms these methods in terms of wirelength and temperature optimization.

For wearable biomedical devices, it is essential to detect target signals under high noise and strong interferences. Moreover, it is critical to realize the system with compact size and easy implementation. To address both goals, this paper presents a chip-based photoacoustic (PA) sensor called QuACL. By leveraging the adaptive coherent lock-in technique, the high sensitivity and specificity can be achieved for detecting target signals. In-phase and quadrature PA templates are specifically designed based on the profile of the target signal and are generated by the FPGA board and the DAC board. The received signal is correlated with the templates to capture, track, and recover the target PA signal. Fabricated in 65-nm CMOS technology, the chip-based sensor system occupies only 0.6 mm2area. The robustness and versatility of the QuACL sensor system are verified by the experiments on discerning and recovering weak PA signals accurately.

Flexible and wearable devices are emerging with the developing of the sensors and IoT (internet of the things). The power consumption and volume of such devices are dominant limitations for wearable feature in various applications. To meet the requirements, a photoacoustic receiver system-on-chip (SoC) is developed and fabricated with a novel correlation detection technique based on the early-and-late tracking. Through this method, output SNR of the receiver can be significantly improved. For this, a low power and high sensitivity analog front-end (AFE) with a noise shaping (NS) SAR ADC is implemented. As oversampling is necessary for the accurate delay of digital processing, noise shaping technique is implemented in the SAR ADC. Simulation results show that, the AFE achieves 70 dB dynamic range and 20 μV sensitivity for about 30 dB output SNR. The SAR ADC can obtain 71 dB SNDR under 50MSps sampling rate with the aid of the NS technique. Based on the analog circuits design, the digital part for the detecting technique is also implemented on chip. The whole power consumption is about 15 mW on the TSMC 65 nm CMOS process.

Long term prediction for generation amount of Converter gas is very important for the optimal scheduling of energy system in iron and steel making enterprises. In this paper, a long term prediction approach based on steelmaking production status estimation is proposed to address this issue. Steelmaking production status estimation has two stages, namely feature extraction and feature fusion. At the first stage, the generation time series of Converter gas is divided into some data segments with the same length, and then a method based on template matching is used to extract the time and frequency domain characteristics of steelmaking production status. At the second stage, an improved version of fuzzy C-mean clustering method is developed for feature fusion, which integrates the characteristics from different data segments to obtain a universal feature of steelmaking production status. Finally, the universal feature is used to reconstruct the generation time series of Converter gas. To verify the effectiveness of the proposed method for long term generation amount prediction of Converter gas, a set of experiments is conducted based on the real world data from an iron and steel enterprise. The experimental results demonstrate that the proposed method exhibits high accuracy and can provide an effective guidance for balancing and scheduling the byproduct Converter gas.