Building large AI fleets to support the rapidly growing DL workloads is an active research topic for modern cloud providers. Generating accurate benchmarks plays an essential role in designing the fast-paced software and hardware solutions in this space. Two fundamental challenges to make this scalable are (i) workload representativeness and (ii) the ability to quickly incorporate changes to the fleet into the benchmarks.

Evaluating the performance of reconfigurable computing applications in multi-tasking systems using simulation (as can be needed in early design-space exploration) faces several challenges. The complexity of full-system, cycle-accurate simulation prevents executing applications of any appreciable size to completion. One must sample only a portion of execution; yet unless care is taken, the measured performance for the sampled interval will not be indicative of the complete execution. Although this is generally a problem for simulation-based evaluation, the problem is exacerbated for multi-tasking systems. This paper therefore presents work to develop a performance evaluation methodology that accurately measures hybrid (both hardware and software) application performance, accounts for additional overhead introduced by hybrid resource management (such as run-time allocation of reconfigurable hardware), and correctly compensates for momentary imbalances in processor time allocation that are only artifacts of the (necessarily) short simulated execution timespan and would balance out over time.

Save and restore of context data is traditionally used in process preemption in multi-tasking operating systems. Multi-tasking, and by consequence, preemption, is key to effective CPU sharing. However, it is much more expensive to save and restore context data in reconfigurable hardware than it is in traditional software. The configuration and current state comprises a large amount of data, making the transfer a long and expensive operation. In this paper, we explore alternatives to the save and restore operation for hardware multi-tasking. We compare the system performance of three alternate policies for reconfigurable hardware kernel preemption in a multi-process system: block, drop and roll. The best-performing policy is able to achieve on average within 4% of the performance of an idealized, zero-overhead save and restore method on a mixed application workload.

Performance evaluation of hybrid (heterogeneous ISA) computing systems faces three major challenges: hybrid execution, multi-tasking, and system-level simulation variation. To evaluate system-level design decisions, a metric must encompass all forms of execution in a system, and incorporate any overheads introduced by hybrid execution. Differences in relative application speedups in a multi-tasking system complicate overall system performance evaluation. In full-system simulation, the relatively limited time-span for feasible tests compounds the evaluation problem. This paper discusses these challenges and presents metrics that address them.

The use of reconfigurable hardware to accelerate computing intensive part of the applications has long been shown to provide large execution speedups. However, the long configuration latency and the limited amount of reconfigurable hardware resources demands careful arbitration of those resources among the applications in the system. In past efforts, we demonstrated that effective allocation of reconfigurable hardware resources can boost overall system throughput in a multi-tasking system. For that work, we invoked reconfigurable hardware scheduling periodically with a fixed interval. In this work, we further examine the size of the static scheduling interval, and propose two adaptive interval approaches that use a phase tracking technique to reduce overall scheduling overhead by up to 85%.

Effective reconfigurable hardware (RH) allocation plays a critical role in multi-tasking systems. Past RH scheduling research has focused on how to allocate RH based on the area and performance of competing hardware kernels. However, these approaches generally assume that the metrics associated with those hardware kernels are pre-determined. However, design-time estimates may not always be accurate or even stable. If the scheduler uses incorrect information, performance of one or more applications will suffer. In this paper, we adapt common performance-monitoring techniques to reconfigurable computing and quantify the importance of active performance monitoring of reconfigurable applications.

Most modern multitasking operating systems assume that, in order to be fair, CPU time should be allocated equally to processes of the same priority. However, this assumption is no longer valid in a system with acceleration hardware, such as reconfigurable hardware (RH), if the goal is equal computation ability for the processes. A process that uses acceleration hardware such as RH can accomplish far more work in a set span of time than a process that only executes on the CPU for that same time. When both accelerated and non-accelerated processes run concurrently, an equal time-slice allocation of CPU resources will not result in equal amounts of work performed. In this paper we present a new allocation technique that distributes computation ability, either equally or with parameterized bias. This technique allows all processes to benefit from RH acceleration—even those that are not specifically designed for it. We demonstrate different possible balancing methods using a custom built Linux kernel with this new scheduler, running on a full-system cycle-accurate simulation platform.

In this paper, we present a full-system reconfigurable computing simulation platform intended to promote innovative new research in reconfigurable computing. Currently, reconfigurable computing researchers frequently use tools such as simple trace-based simulators to provide performance estimates for their designs and methods. However, because the scope of these simulations is generally high-level and limited to the reconfigurable hardware and possibly a host processor, the results presented may unfortunately be less than completely accurate, particularly with respect to memory and processor-hardware communication timing. As reconfigurable computing systems become less theoretical and move closer to widespread realization, more accurate evaluations are necessary to compare new system designs, configuration methods, hardware scheduling algorithms, and hardware structures. We therefore discuss the issues involved in implementing a full-system simulator for reconfigurable computing, presenting specific implementation techniques, and demonstrate the value of reconfigurable computing full-system simulation on an example application

Although many studies have demonstrated the benefits of reconfigurable computing, it has not yet penetrated the mainstream. One of the biggest unsolved problems is the management of the reconfigurable hardware in a multi-threaded environment. Most research in reconfigurable computing has assumed a single-threaded model, but this is unrealistic for personal computing and many types of embedded computing. In these cases, there may be several different threads or processes running simultaneously, each wishing to use the reconfigurable hardware. The operating system must decide how to allocate the hardware at run-time based on the status of the system. The system status could also influence the choice of different implementations for each circuit based on area/speed tradeoffs. This paper examines reconfigurable computing as it could be used in mainstream systems, focusing on a proposed scheduling algorithm to allocate the reconfigurable hardware. Our initial tests indicate that reconfigurable computing with our scheduler can easily achieve at least a 20% system-level speedup.

Although the benefits of software acceleration using reconfigurable logic have been demonstrated repeatedly, this style of computing has not yet penetrated the mainstream. One of the biggest unsolved problems is the management of the reconfigurable hardware in a multi-threaded environment. While most research in reconfigurable computing has assumed a single-threaded model, this is unrealistic for both personal computing and many types of embedded computing. In these cases, there may be several different threads running simultaneously. Each of these threads may have one or more sections of code (kernels) which would benefit from hardware acceleration. Somehow the operating system must decide at runtime which kernels to implement in software vs. hardware based on the status of the system. This includes potentially choosing from multiple possible hardware implementations (with different area/delay tradeoffs) of a single kernel. This paper examines our vision of reconfigurable computing applications in mainstream multithreaded systems, including a presentation of a proposed scheduling algorithm for allocating the reconfigurable hardware.

Due to the ever-increasing complexity of VLSI designs and IC process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. Therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern VLSI designs. In this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. The explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. Experimental results demonstrate that the proposed method exhibits over 100/spl times/ speedup compared with Monte Carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy.

With continuous advances in radio-frequency (RF) mixed-signal very large scale integration (VLSI) technology, the creation of eddy currents in lossy multilayer substrates has made the already complicated interconnect analysis and modeling issue more challenging. To account for substrate losses, traditional electromagnetic methods are often computationally prohibitive for today's VLSI geometries. In this paper, an accurate and efficient interconnect modeling approach-the eddy-current-aware partial equivalent element circuit (EPEEC)-is proposed. Based on complex image theory, it extends the traditional partial equivalent element circuit (PEEC) model to simultaneously take multilayer substrate eddy-current losses and frequency-dependent effects into consideration. To accommodate even larger scale on-chip interconnect networks, EPEEC develops a new simulation program with integrated circuit emphasis (SPICE)-compatible reluctance extraction algorithm by applying sparsification in the inverse inductance domain with an extended window algorithm. Compared with several industry standard inductance and full-wave solvers, such as FastHenry and Sonnet, EPEEC demonstrates within 1.5% accuracy while providing over 100/spl times/ speedup.

We develop parametric modeling and estimation methods for STAP data based on the results of the 2-D Wold-like decomposition. It is shown that the same parametric model that results from the 2-D Wold-like orthogonal decomposition naturally arises as the physical model in the problem of space-time processing of airborne radar data. This correspondence is exploited to derive a computationally efficient parametric partially adaptive detection algorithm. We prove that it is sufficient to estimate only the spectral support parameters of each interference component in order to obtain a projection matrix onto the subspace orthogonal to the interference subspace. The proposed partially adaptive parametric processing algorithm employs this property. The proposed parametric interference mitigation procedure can be applied when only the information in a single range gate is available, thus achieving high performance gain when the data in the different range gates cannot be assumed stationary.