This paper presents a reconfigurable and energy-efficient digital spectrum shaping signaling (DSSS) for multidrop interfaces, where the output spectrum of the transmitted data is shaped using the 2-times repetitive block transmission to avoid frequency notches in the multidrop channel, thereby achieving a data rate up to 4× the first channel notch frequency. In conventional wireline transceivers (TRX), compensating for frequency notches requires a large number of decision feedback equalizer (DFE) taps at the receiver, resulting in significant area and power overhead. In contrast, the proposed DSSS architecture supports spectrum-efficient reconfigurable dual-mode NRZ/PAM-4, reducing required equalization efforts and improving energy efficiency. The proposed scheme and its transmitter (TX) were first validated through event-driven behavioral simulations using XMODEL and verified with equipment-based measurements. Post-layout simulation results in 28 nm CMOS process demonstrated 4 Gb/s data rate communicating over a channel having its first > 30 dB notch at 1 GHz, with a 235 mV vertical eye opening and a TX energy efficiency of 0.39 pJ/b at 0.8 V supply.

This work presents a multi-tone signaling scheme to mitigate the speed and energy consumption bottlenecks in serial data communication systems. The proposed signaling scheme has been developed based on multi-wire spatial domain encoding combined with time domain Hadamard modulation to extend the communication bandwidth. The performance of the proposed scheme will be analyzed and compared to widely used contemporary signaling schemes. The hybrid Hadamard Multi-Tone (HMT) signaling has been developed to improve the bit packing, lower the symbol rate, reduce the channel loss per sub-carrier or sub-channel, and relax the need for equalization, all enhancing efficiency while accommodating high data throughput.

Trade-offs in the design of wideband and energy-efficient inverter-based amplifiers (IAs) will be analyzed and compared to the conventional Current-Mode Logic (CML) based circuits. For a proper comparison, the minimum current consumption of generic IA and the CML amplifiers, with and without active-peaking, will be calculated for a set of target Gain-Bandwidth Product (GBWP) values. This study shows that IAs consume not only lower energy and power compared to their CML counterparts for a given speed specification, but also offer a higher maximum achievable operating frequency. Closed-form expressions, with less than 5% mismatch with simulation results, will be provided to analyze speed-power trade-offs in this type of circuit. This study shows that the consumption of IA circuits (with active peaking) can be lowered by a factor of close to two compared to the CML (with active peaking) in CMOS 28 nm technology, while extending the maximum achievable GBWP by about 12%.

Design of analog circuits is a computationally-complex process. Therefore, robust, simple, and efficient algorithms are required for design automation purpose. Developing generalized analog design methodologies, valid across a large solution space, is very demanding. This article compares computational complexity and precision of three different design methodologies, i.e., gm/ID, Inversion Coefficient, IC, and C/ID, or Inverse-ID approaches. The three methodologies will be analyzed to explore their performance to meet basic needs of the circuit design industry. A basic analog circuit block, i.e., a common-source amplifier, has been selected for this analysis. This study shows that the C/ID method requires the least approximation for optimization.

Herein, a systematic approach for designing loop topology circuits, such as ring oscillators (ROs), latches, and frequency dividers, is proposed. The design flow is devised to implement the target circuits with minimum power dissipation at the desired operating frequency. Using a modified$C/I_{\text {DS}}$methodology, several design examples in different technology nodes are provided showing less than ±5% error in the estimated circuit performance, confirmed by experimental data in 0.18${\mu }\text{m}$technology. A standardized procedure has been developed to extract fundamental device characteristics for different technology nodes, which are subsequently fed into an optimizer script. Examples for implementing current-steering ROs and frequency dividers will be provided. The proposed approach can be employed to custom design high-speed sequential logic circuits, as well as voltage-controlled oscillators (VCOs), digitally controlled oscillators (DCOs), and frequency dividers for applications such as clock generators, sequential circuits, and serial data transceivers in modern integrated systems.

High-order Pulse-Amplitude Modulation (PAM) provides the possibility to enhance the overall data rate in a serial data communication system, while keeping the symbol rate low. The rigid trade-offs between Signal-to-Noise Ratio (SNR) and sensitivity to Inter-Symbol-Interference (ISI), however, put some limitations on the order of PAM, depending on channel response. This article presents a methodological approach, in which different design aspects affecting link budget, such as noise, jitter, and quantization noise, will be studied. A similar procedure, is suggested to be implemented to find the optimal PAM order for different channel responses. Alternatively, this article suggests using a flexible serial data transceiver that can adapt different parameters, including PAM order, depending on channel response and target data rate.

An analytical approach to evaluate performance of analog integrated circuits and make a comparative study in different technology nodes is presented. To provide closed-form solutions, this article proposes using C = C/IDS as an independent design variable, where C refers to any physical or parasitic capacitance associated with a Field-Effect Transistor (FET) biased at IDS. The proposed C-based methodology is used to study speed versus power trade-offs in both continuous-time (CT) and discrete-time (DT) circuits. Predictive Technology Models (PTMs) have been used to study performance of both MOSFET and FinFET (i.e. FET) devices in different technology nodes. This analysis shows that FinFET transistors exhibit a wider medium-inversion region compared to MOSFET devices, making them more convenient for high-speed and low-power designs. Additionally, this study proves that a lower sub-threshold slope factor results in an improved energy-efficiency of analog circuits.

With increasing modulation order, a larger number of parallel source-series-terminated (SST) segments are required to implement precise feedforward equalization (FFE) tap-weight control in SST transmitters (TX). Due to the data routing complexity of the segmented structure, the dynamic power consumption of SST TX has become much more significant causing degradation in energy efficiency. This article presents a 32-Gb/s quarter-rate four-level pulse-amplitude modulation (PAM-4) SST TX with four-tap FFE implemented in 28-nm FDSOI CMOS technology using a high-impedance driver technique to decrease the gate loading of the data path of the SST TX. The output of the whole TX is kept matched to the standard characteristic impedance of the system even though the output impedance of the SST driver alone is high. The high-impedance driver technique decreases the total power consumption by 20% compared to the conventional design by providing a significant reduction in the capacitive load. Our measurement results show that the prototype TX consumes 77.9 mW and achieves an energy efficiency of 2.4 pJ/bit at a 32-Gb/s data rate for PAM-4 signaling.

For an extensive power system network, solving the power-flow problem becomes computationally very burdensome. Current numerical simulators use the iterative approach to find the optimal power-flow state in the power grid, which are prone to numerical instability, convergence issues. Moreover, the existing numerical optimizers are slow, depending on the size and the complexity of the power systems. For massive power grids, large memory consumption and calculation steps are required to find the solution which puts more constraint on the available resources for the processor-based digital solvers. In this paper, a feasibility study of a different methodology is presented, where an alternative analog/mixed-signal circuitry has been introduced to build a custom computer. The proposed accelerator provides the power-flow solution by emulating the actual power system grid inside a miniature VLSI chip. This article demonstrates the feasibility of using a Phase Locked-loop (PLL) based architecture to implement an emulator for a 14-bus system, which reaches to the steady-state condition after 15 μs, exhibiting three orders of magnitude computational speed improvement.

A hybrid analog/digital signal processor has been proposed to implement energy-efficient multi-input-multi-output (MIMO) detectors. A sub-optimum MIMO detector based on Markov Chain Monte Carlo (MCMC) algorithm for a 4×4 MIMO system is presented. The main part of the required signal processing occurs in analog domain to reduce power consumption. The outputs of the proposed analog processor are converted to digital using a low-resolution analog-to-digital converter (ADC) in order to close the loop in digital domain. The proposed 4×4 MCMC MIMO detector is designed in a conventional 45 nm CMOS technology, that consumes 29.3 mW from 1.0 V supply. A throughput of 235.3 Mbps is achieved while operating at 1.0 GHz clock frequency. The design occupies 0.11 mm2silicon area.

An Ultra-Low-Power (ULP) brain interface (BI) circuit, including signal processing front-end (SPFE) and wireless data transmitter (TX), supplied from the incident sensor power, is presented. While a rectifier/voltage multiplier (RVM) provides the required power for the wireless TX circuitry, some of the SPFE circuits are directly supplied from the sensor. This approach helps to reduce the overall required power and simplifies the design of the power management system. The proposed BI circuit is designed in$\boldsymbol{0.18}\ \mu\mathrm{m}$CMOS technology. Isolated Schottky diodes that are available in the process are used to design an RVM for the transmitter block. The SPFE circuitry samples the input, filters the noise and launches the transmitter in case of detecting a sufficient number of target events. The SPFE unit consumes 500 pA from a 400 mV supply, which is provided by the RVM circuit. Data transmission circuitry, which utilizes the same supply, consumes 205 pA leakage power, and$\boldsymbol{2.125}\ \mu\mathbf{A}$average active current during data transmission mode.

A new low-power common-gate continuous-time linear equalizer (CG-CTLE) is presented that exploits active matching termination to increase power efficiency. Also., a new active inductor is proposed., which introduces a higher amount of peaking as compared to the conventional active inductor topologies. The proposed two-stage CG-CTLE is designed in conventional 65-nm CMOS technology using both passive., and the proposed active inductors. These CTLEs compensate for 15 to 21 dB loss of a 12 inches electrical channel while operating within 10-15 Gb/s. Post-layout simulation results show that the CTLEs consume 6 mW and 5.4 mW using passive and active inductors., respectively.

An efficient signaling scheme for serial-data transceivers (TRXs) has been proposed, which can properly reduce inter-symbol interference (ISI) and crosstalk (Xtalk) in memory interfaces. The proposed architecture relies on fully-digital implementation rather than analog/multi-tone approach, which can offer a very power-efficient and versatile silicon implementation. Moreover, the Xtalk induced noise can be fairly reduced by applying the proposed signaling, and the whole TRX can customize to the communication link trough digital calibration, while the aggregate data rate is kept fixed.

The jitter and the phase noise of ring oscillators utilizing subthreshold source-coupled logic (STSCL) style are analyzed in this paper. Closed-form equations are derived to predict the jitter and phase noise caused by white and flicker noise. Measurement results of a test chip fabricated in a standard CMOS 90 nm technology are presented to validate these expressions. The performed analysis shows that jitter in STSCL-based ring oscillator is independent of technology parameters, as opposed to its CMOS counterparts that depend on supply voltage and parameters of technology. Based on measured results, noise on current control line can dominate the total jitter of the oscillator. Design guidelines are proposed to limit the jitter effect of ring oscillators using STSCL logic. The proposed STSCL-based ring oscillator achieves an average RMS jitter as low as 0.24 % of the oscillation period at a 1.08 MHz/μA energy efficiency, which demonstrates its suitability for ultra-low-power applications.

This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed technique is based on using subthreshold source-coupled or current-mode approach for both analog and digital circuits. In addition to possibility of operating with ultra-low power dissipation, because of similar basis for constructing analog and digital parts, a common power management unit could be used for optimizing the power-performance of the entire mixed-signal system. Some circuit examples have been provided to show the performance of the proposed circuits in practice.

The large subthreshold leakage current of static CMOS logic circuits designed in modern nanometer-scale technologies is one of the main barriers for implementing ultra-low power digital systems. Subthreshold source-coupled logic (STSCL) circuits are based on an NMOS differential pair that is switching a constant tail bias current between the two output branches while biased at very low current levels. The power consumption of each STSCL gate depends on the tail bias current that can be controlled very well even for current levels in the range of few tens of pico-Amperes. The precise control on the power consumption of each gate, makes this topology very attractive for ultra-low power applications, where the power consumption of conventional static CMOS system is practically limited by the subthreshold leakage current. In this work, an analytical approach supported by simulation and measurement results will be presented to study the main issues in design of ultra-low power static CMOS and STSCL systems.

This article explores the effect of using source follower buffers (SFB) at the output of source coupled logic (SCL) circuits. This technique can help to improve the power-delay product (PDP) of an SCL gate approximately by a factor of two. The proposed approach has been applied to improve the PDP in sub-threshold SCL circuits that have been developed for ultra- low power applications. Designed in conventional digital 0.18mum CMOS technology, the proposed SCL gate utilizing SFB at the output achieves a PDP of 0.5fJ/fF/gate while the gate draws 10nA from a 0.6V supply voltage.

A fully integrated CMOS base-band part of a low-IF WPAN receiver is presented, which consists of an active complex filter, an automatic gain control unit, and a 10-bit pipeline ADC. The highlights of the receiver include a low-power active complex filter with a new gm-C filter structure and a high-resolution, low power pipeline ADC using averaging and double sampling techniques. The chip was designed using 0.18-μm standard CMOS process. The filter provides more than 55-dB image rejection ratio and IM3 of -50-dB for 0.2-Vpp input signal. The converter has a peak SFDR of 61 dB, maximum DNL of 0.5 LSB, and INL of 0.9 LSB. The whole circuit draws 4-mA from a 1.8-V power supply

In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18 /spl mu/m CMOS process show a THD of less than -44dB for 0.6V/sub pp/ input signal and an input-referred noise of less than 45 nV//spl radic/Hz in worst case. The current consumption of each OTA is 1.5-mA.

A technique to reduce close-in phase noise in CMOS LC voltage controlled oscillators is proposed. In CMOS differential LC oscillators, the up-conversion of flicker noise mainly determines the close-in phase noise. The flicker noise of the bias current is a major component contributing to the overall low frequency noise. In this paper, a switched biasing technique to suppress the flicker noise of the bias circuit is presented. A 1.8V 2.4GHz differential LC VCO is designed in a 0.18mum CMOS technology using this technique. With the proposed switching technique, the close in phase noise is improved as much as 15dB at 500 kHz offset. The simulated phase noise at the offsets of 500 kHz and 1 MHz is -124.6dBc/Hz and -130.3dBc/Hz, respectively. The VCO consumes 2mA from a 1.8v power supply

In this paper, a new frac14 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits is suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18mum CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply

This paper presents an approach to analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition to their acceptable FTOL and flexible topology, have made them very suitable for short-haul multi-rate applications

A fractional multiplying delay-locked loop (FMDLL) for high speed on-chip clock generation applications is presented. The proposed DLL architecture overcomes some drawbacks of phase-locked loops (PLLs) such as jitter accumulation and stability while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier.The output frequency range can be tuned from 1GHz to 2.5GHz with selectable multiplication ratios of M + 0.05 x K where 1 ≤ K ≤ 19. To generate some finer ratios, K could be changed between two consecutive integer numbers. In this situation, a digital delta-sigma modulator could be used to suppress the spurs existing in the output spectrum.

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5 mW/Gbit/s. Statistical simulation is used to estimate the achievable bit error rate in the presence of phase and frequency errors and to prove the feasibility of the concept. VHDL modeling provides extensive verification of the topology. Thermal noise modeling based on well-known concepts delivers design parameters for the device sizing and biasing. We present two practical examples of possible design improvements analyzed and implemented with this methodology.

A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18um digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51mW/Channel/Gbps while occupies 0.045mm2 silicon area

A 1.5 V single supply, fourth order lowpass Butterworth Gm-C filter, on a 0.6 /spl mu/m standard CMOS process is designed. The THD of the transconductor for a 0.7 V/sub pp/ input, is -50 dB at 10 MHz and about -62 dB at 1 MHz frequency. In the proposed transconductor structure, the whole circuit, apart from a DC level-shifter based on a voltage doubler, is biased by a single 1.5 V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70 /spl mu/A current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high frequency response is designed to stabilize the output common-mode voltage. The entire filter chip exhibits an IM3 of -55 dB for 0.6 V/sub pp/ input signals and 1 MHz cut off frequency, with 20 mW power dissipation. The cut off frequency of the filter can be changed from below 1 MHz to about 10 MHz.