Static random access memory (SRAM) plays a critical role in chips due to its high-speed access capabilities, but it suffers from data loss upon power-down and is susceptible to radiation-induced faults. Nonvolatile SRAM (NVSRAM) has attracted substantial research attention for combining the high-speed operation of SRAM with the nonvolatile storage capabilities of emerging memory technologies. This article proposes a 12T2R NVSRAM cell based on resistive random access memory (RRAM), achieving nanosecond-scale data backup and recovery. The novel design integrates an independent RRAM operation path and an SRAM power-gating switch, ensuring reliable backup and low-power sleep mode. Building on the memory array, the system further integrates a power management module, control and driver circuitry, and a dual-layer error correction code (ECC) strategy. This holistic co-design across device, circuit, and architecture levels delivers enhanced reliability, energy efficiency, and fault tolerance. Simulation results under 65 nm CMOS process demonstrate significant improvements in key performance metrics, including speed, power consumption, noise margin, store/restore yield, and bit error rate (BER). All functional modules meet the design specifications, with markedly improved data backup and restoration success rates, providing a promising solution for next-generation high-performance nonvolatile memory (NVM) systems.

Computing-in-Memory (CIM) with ReRAM crossbar arrays accelerates Deep Neural Network (DNN) computations by executing operations directly within memory, which reduces both data movement and energy consumption. Recent studies show that lowering the precision of Analog-to-Digital Converters (ADC) in crossbar peripheral circuits can significantly reduce system area and power overheads at the risk of increasing quantization-induced numerical errors that degrade inference accuracy. This paper proposes a Boundary-Aware Regularized Quantization (BARQ) technique to maintain accuracy in CIM accelerators with low-precision ADCs. BARQ introduces ADC bit-width boundary constraints to regulate model weights during quantization-aware training (QAT), mitigating overflow-induced clipping errors and enhancing unstructured weight sparsity. Additionally, we introduce a novel weight initialization strategy based on Euclidean projection, which minimizes initial quantization error and facilitates faster and more stable convergence. Experiments on the CIFAR-10, CIFAR-100, and ImageNet datasets show that BARQ achieves minimal accuracy loss of only 0.59% even with 3-bit ADCs. Furthermore, by enhancing weight sparsity, BARQ further reduces energy consumption by up to 75% and improves hardware efficiency by 3.79× compared to conventional quantization methods.

Abstract Efficient and accurate template matching in multisource images is a difficult task when hardware platform resources are limited. Motivated by the problems encountered in present methods, a template matching scheme, called Matching by Pixel Distribution Comparison (MPDC), is proposed to reduce the use of system resources by combining traditional algorithms and neural networks. The MPDC scheme first extracts the distribution information of image pixels through the developed extended Slice Transform (eSLT) matrix to overcome the non‐linear intensity difference between heterogeneous images. Then the similarity between heterogeneous images is evaluated by comparing the pixel distribution rules reflected by the eSLT matrix. A similarity score table is constructed based on the pixel distribution comparison, and the similarity score between heterogeneous image pairs can be calculated by querying this table. The comparison of eSLT matrices can be completed through either experience scoring or neural network learning. The experimental results show that, on a hardware platform with limited resources, the 64 × 64 template can be matched by sliding on the 256 × 256 query image in 2.85 s, and it only takes at least 19.84 s for neural network training on the CPU. The matching performance is also better than many popular multisource image algorithms.

Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm technology due to the scaling of the transistors. High soft error rate is caused by particle striking at cells and logic circuit in SRAM. This work proposes an SEU robust dual access 12T (DA-12T) SRAM with a radiation hardened crossbar-based peripheral circuit (CBPC). The proposed cell with 209% area penalty is more SEU robust than most cells. The CBPC can reduce the read failure rate of SRAMs. The new sense amplifier ensures the correct and rapid reading operation speed when suffering read disturbance. The experiment results show that the SEU cross-section of proposed cell is 60% of standard cell with dummy. Almost no read failure is observed in SRAM with CPBC when operational frequency exceeds 40MHz. Further investigation indicated that DA-12T cell and well isolation technique can reduce the read failure rate.

Although the magnetic tunnel junction (MTJ) is intrinsically immune to radiation, the read/write operations of magnetic random access memory (MRAM) may be vulnerable to radiation-induced current. In this paper, we investigate the radiation hardening design for spin orbit torque based MRAM (SOT-MRAM). The hardening technique is firstly studied at the device level by optimizing the dimension and magnetic parameters. Then we propose radiation hardening read and write circuits addressing the influence of single event upset (SEU). Based on a physics-based SOT-MTJ compact model and a 65nm CMOS design kit, simulation results show that the proposed MOS-stacked read sensing amplifier and write circuits of six PMOS transistors as a feed-back structure to charge/discharge sensitive nodes can correct soft errors.

SRAM-based FPGAs have been widely used in space engineering. However, the configuration memory in SRAM-based FPGA is susceptible to the single event effects (SEE). It can disrupt the communication or control functions of the spacecraft. To mitigate SEE effects of the SRAM-based FPGAs used in space radiation environment, Beijing Microelectronics Technology Institute (BMTI) developed a 300 thousand gates Single Event Effect hardened SRAM-based FPGA -- BQVR300RH. The BQVR300RH employs Radiation Harden by Design (RHBD) technique. Hardened standard cell library based on Adaptive SRAM (ASRAM) structure is established. For especially sensitive and important resource, other assistant techniques are also adopted. The experiment results show that the BQVR300RH improved the anti-SEU characteristic a lot, compared with Xilinx 300 thousand gates space-grade SRAM-based FPGA (XQVR300). The SEU threshold of BQVR300RH is 19.06 MeV⋅cm2/mg. The anti-SEU characteristic improves three orders of magnitude than XQVR300. The improvement of anti-SEU behavior expands the usage of SRAM-based FPGA in aerospace applications. Currently, BQVR300RH has been used in space field in China.

The programmability of an FPGA poses a number of challenges when it comes to complete and comprehensive testing of the FPGA itself. A large number of configurations must be downloaded into the FPGA to test the programmable sources. A great many methods were proposed to reduce the number of configurations to minimize the test time, but few of papers were focus on reducing single configuration time. This paper proposes a novel method to reduce more than 30% of the total configuration time based on partial reconfiguration technology and sorting algorithm. This method is implemented on a series of SRAM-based FPGAs. The experimental result shows that this method reduces 30%-45% of the total configuration time and can be generally applied to all SRAM-based FPGAs currently.

The significance of FPGA test and the challenge of its increasing cost can never be ignored. In island-style FPGA architectures, hex lines are the principal interconnect resources. Testing hex lines and hex Programmable Interconnect Points (PIPs) have remained as the major technical difficulty in FPGAs test due to complex interconnect rules. Particularly, test in oblique direction of hex PIPs has rarely been addressed in previous studies. Towards this challenge, this paper for the first time proposes a coordinate system and formulates the interconnect rules of hex lines as mathematical equations. For hex PIPs in horizontal and vertical direction, an efficient circle test structure is formed by coordinate equations. For hex PIPs in oblique direction, the coordinate method is used to generate the partial-cascade pattern. The corresponding test vector is also generated, which ensures the ergodicity of hex PIPs in oblique direction. In addition to hex PIPs, hex lines are also covered without extra effort. Compared to previous researches, the configuration number for hex lines is decreased significantly. We evaluate this method on Xilinx XC2V1000, and experimental results show that our proposed method achieves 100% fault coverage for hex PIPs and can be generally applied to all mainstream island-style FPGAs with a similar interconnect structure currently.

Reconfigurable system-on-a-chip(SoC) is an important trend of embedded system. It is not only to achieve a higher performance but also flexible enough. In this paper a new kind of reconfigurable system using SoP(System on a Package) technology is presented and a new kind of peripheral bus which is used to form a whole system architecture is proposed based on the reconfigurable system. Using this peripheral bus, we can form a new embedded system easily by changing different intellectual property(IP) cores. We can make the whole system much more smaller, higher levels of integration, lower costs and lower power by using this chip and the peripheral bus. Compare with the earlier system, the new system using the reconfigurable chip which is of the same function is much smaller and lighter. All these are very suitable for small satellites and consumer electronics.

A 1.0-V, 50-mA capacitor-less low-dropout (LDO) voltage regulator with 100pF internal output capacitor for SoC applications is presented. The proposed LDO makes use of a bi-directional asymmetric buffer (BDAB), which provides a signal inversion feedback path and a signal non-inversion feedforward path with different magnitudes at the same time. The feedback path can perform frequency compensation and transient enhancement, while the feedforward path can improve the stability and increase the unit-gain frequency (UGF) by removing right-half-plane (RHP) zero. Simulation results show that the LDO has robust stability, high UGF (up to 1.7-MHz even at no-load), and excellent transient response performance. The overshoot and undershoot of the output voltages are less than 100-mV when the load step changes between 0 and 50-mA in 1-μs, the settling time is 2-μs, while the dropout voltage is 100-mV at full-load current.

A novel scheme is presented for achieving high performance low-dropout (LDO) voltage regulators under the constraint of low supply voltage. This scheme makes use of a frequency-dependent feedback factor (FDFF). The FDFF has simple circuit structure and frequency-dependent gain. When it is used in the proposed LDO, the low voltage operation ability, wide-band high power-supply rejection (PSR) characteristic and excellent transient response performance can be obtained. Simulation results show that this LDO can work properly at 1.2-V supply voltage, and the overshoot is only 1mV, while the PSR is better than 40dB from dc to 100-MHz. Therefore, the FDFF based LDO is well suited for low-voltage ripple-sensitive applications.