This work introduces a heart disease classification system. The system includes electrocardiography (ECG) arrhythmia classification and phonocardiography (PCG) heart-valve diseases classification algorithm, achieving 97.4% and 99.1% accuracy. Additionally, the paper presents a procedure for lightweight convolutional neural network (CNN) model quantization with an 8-bit fix-point and 0.1% accuracy loss. Furthermore, this study proposes a programmable artificial intelligence (AI) accelerator with an application-specific instruction set processor (ASIP) and systolic array architecture to achieve high-performance computing. Moreover, we introduce a matrix mapping unit (MMU) and the pipeline state register (PSR) to facilitate switching between CNN and matrix multiplication, resulting in a reduction of over 50% in timing overhead. The chip is implemented on Xilinx’s PYNQ-Z2 and achieves a power consumption of 106 mW, with a classification latency of 6.8ms / 21ms (arrhythmia/valve diseases).

This work proposes an arrhythmia classification system. The algorithm includes naive electrocardiography (ECG) data preprocessing procedures that apply to various ECG databases. Additionally, the paper presents an ultra-lightweight model designed for arrhythmia classification, which combines a Convolutional Neural Network (CNN) with long-term heart rate information to enhance the performance of the model. The proposed model was trained and tested using the MIT-BIH and NCKU-CBIC database, following the classification standards of the Association for the Advancement of Medical Instrumentation (AAMI), achieving an accuracy of 98.5% and 97.1%. Furthermore, this work proposes a customized artificial intelligence (AI) accelerator for hardware implementation, which leverages a parallelized processing element (PE) array architecture and hybrid stationary techniques to achieve high-performance computing. The chip implementation achieves a power consumption of 122 μW, a classification latency of 6.8 ms, and an energy efficiency of 0.83 μJ/classification.

This paper proposes a voltage-controlled oscillator (VCO)-based $2^{\mathrm{n}\mathrm{d}}-$order continuous-time delta-sigma modulator (CTSDM) for current-sensing readout systems. The proposed VCO-based CTSDM can immediately quantize the current signal from sensor without pre-amplifier. A proportional-integral (PI) structure has been realized by injecting a resistor in series with the integrating capacitor to simplify the circuit complexity as well as maintain the system stability. A noise shaping with second order is implemented by the first-stage PI current integrator and a second-stage VCO phase integrator. The complementary current-steering digital-to-analog converter is adopted as the feedback path for the current subtraction. Simulation results show that the proposed current-sensing VCO-based CTSDM can achieve a signal-to-noise-and-distortion ratio (SNDR) of 81.36 dB in 10 kHz bandwidth while consuming only 13.2 $\mu$w under 1.2 V supply. This corresponds to a Figure-of-Merit (FoM) of 170.15 dB which is suitable for sensor readout applications in internet of thing (IoT).

A 3rd-order feedforward high-pass sigma-delta modulator (HPSDM) with operational amplifier (op-amp) sharing and noise-coupling techniques is presented in this paper. The modulator is suitable for biomedical signal acquisition with features of high resolution and low power consumption. Op-amp sharing technique has been utilized to reduce the number of amplifiers. To add an additional noise-shaping order, the noise-coupling technique is embedded in the summing stage without additional amplifier. To overcome the circuit sensitivity to process variation and capacitor mismatch, a new high-pass integrator structure is proposed. Simulation results reveal a Signal-to-Noise and Distortion Ratio (SNDR) of 79.64 dB consuming 1.31 $\mu$W under 1.2 V supply voltage, which can achieve peak Schreier Figure-of-Merit (FoM) of 161.64 dB and peak Walden FoM of 0.4 pJ/conv.

A high-pass sigma-delta modulator (HPSDM) that uses operational amplifier (op-amp) sharing and programmable feed-forward coefficients is presented for an electrocardiography (ECG) signal detection system. Op-amp sharing is used to reduce the quantity of amplifiers because they dominate the entire power consumption of the HPSDM. Moreover, the amplitude of the ECG varies from person to person; hence, programmable feed-forward coefficients are used to adjust the dynamic range of HPSDM to obtain high resolution across users. This technique is implemented using the 0.18 μm standard CMOS process. Measurement results reveal that the proposed HPSDM has a signal-to-noise and distortion (SNDR) of 54.5 dB and a power of 2.25 μW under a 1.2 V supply voltage to achieve the figure of merit of 12.96 pJ/conv. In terms of other settings, the proposed HPSDM has an SNDR of 64.8 dB and a power of 5.2 μW under a 1.8 V supply voltage to achieve the figure of merit of 9.15 pJ/conv. Both modes extend the dynamic range of 12 dB according to the programmable feed-forward coefficients.

This paper proposed an intelligent stethoscope, which can not only visualize the heart sound signal, but also measure human's electrocardiogram (ECG) and heart sound simultaneously. With an internet of things (IoT) system and a cloud database, the stethoscope can be used in hospitals and telemedicine. The proposed stethoscope includes three parts, a front-end device for ECG and heart sound measurement, a smart device's APP and a cloud server. The ECG-measuring device is designed for single lead measurement and it has low power consumption as well as IoT-based design, which can send the real-time ECG data to the smart device's APP. On the other hand, the heart-sound-measuring device keeps the traditional stethoscope head, in order to ensure doctors can be used to the heart sound signal from this proposed stethoscope. Furthermore, it is attached an analog front-end circuit and a microphone, to filter the environmental noise and record the sound signal. At the end, the heart sound signal will be transmitted to the APP through the module of Bluetooth Low Energy (BLE). The APP on smart device can display the synchronized and real-time signals including ECG and heart sound. Meanwhile, those signals will be recorded in smart devices and uploaded to the cloud server, where doctors and users can further monitor the data. The cloud server can not only store the past signals, but also realize telemedicine through the web user interface. The proposed intelligent stethoscope has been conducted human trials in the National Cheng Kung University Hospital.

This study presents an intelligent stethoscope that can visualize heart sound signals and can simultaneously measure human's electrocardiogram (ECG) and heart sounds. The proposed stethoscope can be used in hospitals and telemedicine through an internet of things (IoT) system and a cloud database. The proposed stethoscope includes three parts, namely, a front-end device for ECG and heart sound measurement, a smart device application (APP), and a cloud server. The ECG-measuring device is designed for single lead measurement and has low power consumption and IoT-based design, which can send real-time ECG data to the smart device APP. Simultaneously, the heart-sound-measuring device combined with a traditional stethoscope head is used to measure heart sound signals. This device includes an analog front-end circuit and a microphone to filter environmental noises and to record heart sound signals. Heart sound signals are transmitted to the APP by using a Bluetooth Low Energy module. The smart device APP can display synchronized and real-time signals, including ECG and heart sounds. Meanwhile, those signals are recorded in smart devices and are uploaded to the cloud server, where doctors and users can diagnose and monitor healthcare anytime. The cloud server can store previous signals and can realize telemedicine through a web user interface. The proposed intelligent stethoscope is applied on human trials in the National Cheng Kung University Hospital.

In this paper, a high-efficiency rectifier and a low temperature coefficient (TC) bandgap voltage reference (BGR) in energy-harvesting circuits are presented. The audio signal generated from smartphone is used to verify the energyharvesting circuits that are composed of a full-wave low-voltage active rectifier, a low-dropout (LDO) regulator, and a currentmode BGR circuit. An active diode and a proposed AVC are presented to enhance the rectifier efficiency. The rectifier output voltage is regulated by an LDO close to a stable 1.2-V supply voltage in a 0.18-μm 1P6M Taiwan Semiconductor Manufacturing Company standard complementary metal-oxide- semiconductor (CMOS) process. A curvature-compensation technique is proposed to improve the TC of the BGR, and the best TC of 15.33 ppm/°C between the temperature range of -10 °C and 120 °C is measured. The measured rectifier achieves the maximum power conversion efficiency (PCE) of 87.2% under 1.77 Vppac input signal with 2-kΩ output load resistance. The measured results demonstrate the better characteristic of the rectifier and BGR than that of previous works using the low-power structure.

A smart pet clothing with full hardware and software support for internet of things is proposed. The hardware comprises three parts: a special pet sensor, an analog front-end circuit for detecting electrocardiogram (ECG) and breath signals, and a micro printed circuit board with signal communication. The software also consists of three parts: an algorithm for biosignal processing, an application (app) as graphical user interface (GUI), and a web server for healthcare. The algorithm is used to calculate the heart rate (HR), HR variability (HRV), high-to-low-frequency ratio determined by HRV analysis, breath rate, and basic emotion analysis. The app is developed for building a user-friendly GUI and communication platform between the hardware device and the cloud server. The web server not only provides detailed information to the veterinarian and the pet owner but also runs a convolutional neural network algorithm on big data to identify abnormal ECG signals. The analog front-end circuits with ECG and breath detectors, an ARM Cortex M0 MCU, and Bluetooth and power modules are integrated into a device with the size of a coin that can be placed in an approximately 32 mm × 32 mm × 24 mm box. The mechanism can be easily worn on clothing for monitoring pet health and mood.

This paper presents a novel calibration technique for charge redistribution digital-to-analog converters (DACs). By using the proposed clock-pulse-width calibration, the clock of the DAC is modulated, and the output voltage is effectively modified to enhance the differential-non-linearity (DNL) and integral-non-linearity (INL). By using this method, the measured DNL, and INL have been improved by 61% and 87%, respectively. This calibration is done in few steps, and is aided by a cyclone IV FPGA and an ADC. The DAC has been manufactured in a TSMC 90 nm CMOS process, with a core area of 0.011 mm2. The supply voltage, power consumption, and clock frequency of the IC are 1.2 V, 371 uW, and 8 MHz, respectively.

A bladder neuromodulation with a system controller and microstimulator is proposed. The system controller is used for transmitting the stimulating parameters with four functions: fetching, decoding, calculating, and outputting. The fetching circuit receives series parameters from a phase-shift keying demodulator. The decoding circuit decodes the data for the stimulus parameter. The calculating circuit is used to count the timing, which has the timing information of the stimulation for monophasic, charge-balanced biphasic, charge-imbalanced biphasic, and charge-balanced biphasic with delay. The outputting circuit is a finite state machine with four states: anode pulse width, pulse delay width, cathode pulse width, and burst period width. The microstimulator consists of a digital-to-analog converter (DAC) and a stimulus generator circuit. The DAC is a commercial current-mode 8-bit chip. The stimulus generator circuit is realized in a field-programmable gate array to provide the required stimulation current for tissue. The controller is implemented by the TSMC 0.18 μm 1P6M CMOS process. The whole area of the chip is 1.44 mm2 and has a power consumption of 29.7 mW at 1.8 V supply. An animal study is conducted to demonstrate the circuit function and to verify the effect of micturition according to current stimulation.

With shrinking process technology, decreasing supply voltage, and increasing clock frequency, noise reduction becomes more and more crucial to the success of modern mixed-signal system-on-chip design. To eliminate the switching noise due to crosstalk coupling between analog and digital signals, it is essential to fully separate the routing paths of analog and digital nets when generating mixed-signal layouts. Different from previous works which cannot fully separate analog and digital routing paths, this paper presents a novel hierarchical deterministic mixed-signal layout synthesis approach with the separation of analog and digital signal paths for switching noise elimination. Experimental results based on a third-order Σ Δ modulator show that the proposed approach can result in various layouts with separated analog and digital signal paths while achieving better signal-to-noise and distortion ratio, and overall performance specifications.

This paper presents a low-power energy-harvesting circuit with error-correction demodulation for radio-frequency identification (RFID) application. This circuit uses the new structure to demodulate ASK signals and includes the power unit with a wake-up circuit and a power-on-reset controller. The energy-harvesting circuit proposed by this paper can substantially decrease the capacitance used in the demodulator circuit and the wake-up circuit, and the capacitance is 14 pF only. Moreover, a detection circuit and a correcting circuit are adopted to enhance bit error rate of decoding. The chip was implemented in CMOS 0.18 μm technology. The sensitivity of this work is -13 dBm. The pulse width error can be reduced to less than 1% to fit the EPC Gen-2 standard by error-correction demodulator.

A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process.

This paper presents a wireless biosignal acquisition system-on-a-chip (WBSA-SoC) specialized for electrocardiogram (ECG) monitoring. The proposed system consists of three subsystems, namely, 1) the ECG acquisition node, 2) the protocol for standard IEEE 802.15.4 ZigBee system, and 3) the RF transmitter circuits. The ZigBee protocol is adopted for wireless communication to achieve high integration, applicability, and portability. A fully integrated CMOS RF front end containing a quadrature voltage-controlled oscillator and a 2.4-GHz low-IF (i.e., zero-IF) transmitter is employed to transmit ECG signals through wireless communication. The low-power WBSA-SoC is implemented by the TSMC 0.18-μm standard CMOS process. An ARM-based displayer with FPGA demodulation and an RF receiver with analog-to-digital mixed-mode circuits are constructed as verification platform to demonstrate the wireless ECG acquisition system. Measurement results on the human body show that the proposed SoC can effectively acquire ECG signals.

This paper presents a wide-band low-power super-heterodyne RF front-end for the Medical Implant Communications Services (MICS) band. The front-end consists of a low-noise amplifier (LNA), a mixer, buffers, and passive baluns. The proposed circuits feature the techniques of current-reuse, MOSFET back-gate coupling, feedback, and current bleeding to achieve low power under acceptable noise figure (NF) levels for the MICS application. The RF front-end is implemented in 0.18um standard CMOS process with an area of 1.4mm×1.2mm at a supply voltage of 1.8V. Measurement results reveal the capability of a minimum sensitivity of -97dBm, maximum conversion gain of 30dB, and total noise figure (NF) of 11.6 and 13.2 dB while consuming 1.3mW and 2.9mW, respectively.

This paper presents a high-efficiency rectifier and low-dropout regulator (LDO) for a body area network. The rectifier receives signal for energy harvesting, and the LDO is employed to generate stable supply voltage. The rectifier uses bootstrapped capacitors and adaptive voltage controller to reduce threshold voltage and to improve further the power conversion efficiency (PCE). The LDO combines voltage buffer, pole-zero tracking, and pseudo resistor technologies to achieve low quiescent current and precise output voltage. This chip has been fabricated by using the TSMC 0.18 µm 1P6M CMOS technology. The core area is 0.1 mm2. Circuit-level simulation reveals that the PCE of the proposed rectifier is 90.7% when the input peak-to-peak voltage is 2.3 V, the output load is 2 kΩ, and the quiescent current of LDO is 15.27 µA.

This demonstration will present a wearable and wireless bio-signal acquisition and classification system that is specialized in electrocardiogram (ECG) monitoring. The system comprises the design and implementation with three parts, namely, an analog front-end (AFE) circuit, a digital signal processor (DSP) and the Bluetooth module. The AFE is used to detect the ECG signal and DSP is used to classify the signal and control the Bluetooth communication. At last, the real time ECG signal would be shown on the screen of the mobile phone. The system is implemented in a TSMC 0.18μm 1P6M process under supply voltage of 1.2 V. With two PR44 zinc-air batteries of 605mAh as the power supply, the system can be operated about 2 days.

A fast Fourier transform-based (FFT-based) foreground digital calibration method for multistage pipeline analog-to-digital converter (ADC) is proposed in this paper. The calibration method can overcome the capacitor mismatch and finite gain of the operational amplifier (OPAMP). Given that the capacitor mismatch and finite OPAMP gain cause the radix of all the stages of multistage pipeline ADC to become unequal to 2n, the FFT processor can be adopted to evaluate the real radixes of all the stages and generate new digital output to compensate the error caused by these nonideal effects. Moreover, because capacitor mismatch and the finite gain of OPAMP can be compensated, low-gain OPAMP can be used in high-performance ADC to reduce the power dissipation, and the small capacitor can be adopted to save the area. An example of a 10-bit 1.5-bit/stage pipelined ADC with only an 8-bit circuit performance is implemented in 0.18 μm TSMC CMOS process. The circuit measurement result reveals that the signal-to-noise-and-distortion ratio (SNDR) of 51.03 dB with 11-dB improvement after calibration can be achieved at the sample rate of 1 MHz.

In analog layout design, the accuracy of capacitance ratios correlates closely with both the matching properties among the ratioed capacitors and the induced parasitics due to interconnecting wires. However, most of the previous works only emphasized the matching properties of a common-centroid placement, but ignored the induced parasitics after it is routed. This paper addresses the parasitic issue in addition to device matching during common-centroid capacitor layout generation. To effectively minimize the routing-induced parasitics, a novel common-centroid placement style, distributed connected unit capacitors, is presented. Based on the placement style, the ratioed capacitor layout generation flow and algorithms are proposed to simultaneously optimize the matching properties of a common-centroid placement and minimize the induced parasitics. Experimental results show that the proposed approach can greatly reduce area, wirelength, and routing-induced parasitics, and guarantee the best matching quality after routing.

A 2.4 GHz fully integrated CMOS RF front-end with low-noise amplifier (LNA), differential power splitter (DPS), and quadrature mixer based on current-reused folded architecture is proposed. The circuit has been implemented to fit the specifications of IEEE 802.15.4 2.4 GHz standard. To address the low power consumption issue, the active differential power splitter is directly stacked upon the LNA to allow the reuse of the DC bias current. The folded structure is implemented by using the PMOS device as the quadrature mixer to achieve low flicker and thermal noise, simultaneously. Both the LNA and the DPS are biased in the subthreshold region, which can offer superior gain per current consumption as compared with operation in the strong-inversion region. The chip is fabricated in the 0.18 µm CMOS process with an area of 1.69 mm2at a supply voltage of 1.2 V and power consumption of 1.08 mW. Based on the measurement results, the conversion gain of 20.5 dB and S11 of −17 dB can be obtained, respectively. Moreover, the IIP3 in the whole chip is −7.8 dBm, and the total double-side band noise figure is 13.2 dB.

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

Through an integration of wireless communication and sensing technologies, the concept of a body sensor network (BSN) was initially proposed in the early decade with the aim to provide an essential technology for wearable, ambulatory, and pervasive health monitoring for elderly people and chronic patients. It has become a hot research area due to big opportunities as well as great challenges it presents. Though the idea of an implantable BSN was proposed in parallel with the on-body sensor network, the development in this area is relatively slow due to the complexity of human body, safety concerns, and some technological bottlenecks such as the design of ultralow-power implantable RF transceiver. This paper describes a new wireless implantable BSN that operates in medical implant communication service (MICS) frequency band. This system innovatively incorporates both sensing and actuation nodes to form a closed-control loop for physiological monitoring and drug delivery for critically ill patients. The sensing node, which is designed using system-on-chip technologies, takes advantage of the newly available ultralow-power Zarlink MICS transceiver for wireless data transmission. Finally, the specific absorption rate distribution of the proposed system was simulated to determine the in vivo electromagnetic field absorption and the power safety limits.

A wireless ECG detection system with a low-power analog front-end (LPAF) circuit and a Bio-processing ZigBee (BioZigbee) firmware is presented in this paper. The LPAF circuit comprises an ECG signal acquisition board and a low-pass filter to capture and filter the physical ECG signals from the human body. The low-pass filter in the proposed LPAF circuit is fabricated using the 0.18 μm TSMC CMOS process technology. Its aim is to operate under a supply voltage of only 1 V and a total power consumption of 453 nW. The BioZigbee firmware consists of programs that internally control various electronic devices including the analog-to-digital converter (ADC), the ECG compressor, and the ECG coordinator on the transmitter/receiver to convey the captured ECG signals efficiently and correctly. Results show that the LPAF circuit and BioZigbee firmware work together to perform effective and reliable ECG signal acquisition, processing, and communication.

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. With attention to power-efficient communication in the body sensor network, RF power transfer was estimated and the required low-power ICs, which are important in the development of a healthcare system with miniaturization and system integration, are discussed based on the RFID platform. To analyze the power transformation, this paper adopts a 915-MHz industrial, scientific, and medical RF with a radiation power of 70 mW to estimate the power loss under the 1-m communication distance between an RFID reader (bioinformation node) and a transponder (biosignal acquisition nodes). The low-power ICs of the transponder will be implemented in the TSMC 0.18-μm CMOS process. The simulation result reveals that the transponder's IC can fit in with the link budget of the UHF RFID system.

In this paper, a 1-V 8-bit 10 kS/s successive approximation (SA) analog-to-digital converter (ADC) with ultra-low power characteristic is implemented for biosignal acquisition systems. To decrease power consumption, a passive sample-and-hold (SH) circuit and an opamp-free, capacitor-based digital-to-analog converter (DAC) are utilized. The only active circuit, a comparator, is implemented in the sub-threshold region to preserve the required bias current. According to the measured results, the ADC has a signal-to-noise distortion ratio (SNDR) of 45.2 dB, and peak spurious free dynamic range (SFDR) of 54 dB for a 1 kHz 500 mVppinput sine wave. The effective number of bits (ENOB) is 7.2. Its differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.41/+0.38 and −0.89/+0.6 LSB, respectively. The total power consumption is 950 nW, and the figure of merit (FOM) is 3230 fJ/conversion-step. The active area, which is 0.93 × 0.93 mm2, is determined by using TSMC 0.18µm 1P6M CMOS process.

An ultra-low voltage and low-power adaptive switched-current sigma-delta modulator (SISDM) with a 10-bit dynamic range for bio-microsystem applications is presented. In order to achieve the low-voltage requirement, a novel class-AB switched-current memory cell is adopted to implement the SISDM with the over-sampling ratio (OSR) of 64. In addition, a proposed differential current comparator and a low-voltage 1-bit switched-current digit-to-analog converter (SIDAC) are used for the design of the SDM. Benefits from the SISDM using the class AB memory cell are low-power consumption, high linearity, and high dynamic range. For the various applications with different biosignal frequencies, the SISDM could be operated in different operation mode. The overall SDM with core area of 0.05mm/sup 2/ has been implemented in a TSMC 0.18/spl mu/m 1P6M standard CMOS process technology. Without voltage booster to raise the gate voltage of switches, post-layout simulation results show that the SISDM has a dynamic range over 60dB and a power consumption of 180/spl mu/W with an input signal of 1.25kHz sinusoid wave and 5kHz bandwidth under a single 0.8V power supply for ENG signals.

A simple addressing scheme for pipeline MDC shared-memory architecture with mixed-radix algorithm is proposed. It can provide a simple control circuit for memory addressing generation, and the mixed-radix butterfly sequence can be automatically generated by way of simple counter. In addition, for the N-point FFT processor, only N/8 coefficients should be stored in the VLSI implementation, therefore, the ROM size and the FFT processor area are reduced. According to the simple control scheme and small memory size, the low-power VLSI architecture can be achieved. Furthermore, the architecture with the mixed-radix algorithm also enhances the speed in performing large-point FFT computations compared with the existing shared-memory architectures. Based on this architecture, not only radix-2/sup 3/ butterfly is adopted to achieve the requirement of high throughput, but also radix-2/sup 2/ or radix-2 butterfly is utilized to allow all of FFT calculation for N=2/sup n/. An VLSI architecture of 8192-point FFT processor with only power consumption of 890/spl mu/W is also implemented to demonstrate the proposed method.

Two programmable FFT processors for OFDM (Orthogonal Frequency Division Multiplex) communication systems are presented in this paper. Coolay-Tukey radix-2/4/8 algorithm and mixed-radix-2/22/23 are employed in the pipelined SDF (Single-path Delay Feedback) architecture and pipelined MDC (Multiple-Path Delay Commutator) shared-memory architecture, respectively. The size of FFT processors with power of 2 can be programmable in the range between 64 and 8192. Based on the programmable SDF architecture, an FFT processor with 64/128-point has been implemented under the TSMC 0.35mm CMOS technology. Its core area is 1.6*1.6mm2 and the power consumption is 340mW. Moreover, a simple addressing scheme for pipelined MDC shared-memory architecture with mixed-radix algorithm is also proposed to achieve the programmable object. It can provide a simple control circuit for memory addressing generation, and the mixed-radix butterfly sequence can be automatically generated by way of simple counter. In addition, for the N-point FFT processor, only N/8 coefficients should be stored in the VLSI implementation, therefore, the ROM size and the FFT processor area are reduced. According to the simple control scheme and smaller memory size, the low-power VLSI architecture can be achieved. Furthermore, the architecture with the mixed-radix algorithm also enhances the speed in performing large-point FFT computations compared with the existing shared-memory architectures. Based on this architecture, not only high radix-23 butterfly is adopted to achieve the requirement of high throughput, but also low radix-22 or radix-2 butterfly is utilized to allow all of FFT calculation for N=2n. An VLSI architecture of 8192-point FFT processor with only power consumption of 890mW is also implemented to demonstrate the proposed method.

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs current reuse and double frequency circuits in the RF input stage and LO stage, respectively, to improve its linearity and isolation. In addition, the proposed topology has the advantage of the low power consumption. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of conversion gain and linearity have been described in details. The measured results reveal that the proposed mixer possesses single-end conversion gain of 8 dB and third-order input intercept point (IIP 3) of –3.8 dBm, respectively, under the supply voltage of 1.8 V and LO power of 4 dBm. The power consumption of the proposed mixer is about 1.4 mW at 900 MHz.