A new system which automatically sizes and places CMOS analog cells is presented.Unlike most previous works, we have focused on general rules and algorithms which suit any type of operational amplifier.Our approach can be described in three main parts.The first part is a pattern recognize based on electrical considerations which, given a Spice netlist, identifies basic subcircuits.This information is used in the jirst loop of our optimizer.Together with the target specified by the user, it results in electrical constraints used to define a good starting point in the sizing process.Classical algorithms of optimization can then be used.The same information is also an input to the placement.It results in a set of topological constraints used for the generation of the basic elements, and their relative placement.This package is actually used be analog designers to quickly enter new structures and adapt them to their needs.Some design examples are reported.

A switchbox router utilizing layers is presented. Each net is first partitioned into a set of subnets. This decomposition is driven by the minimum Steiner tree. The construction is then carried out on a step-by-step basis, which allows the system to dynamically take new information on the problem into account. The information is examined by a set of expert systems which decide which subnet should be routed next. This part has been implemented with a blackboard architecture. The router can handle pins that are not on a grid on one set of parallel edges. The program has been implemented in the LISP programming language. Many test cases have been run successfully, and some results, including Burstein's difficult switchbox, are presented.>

A new routing region definition and ordering algorithm are presented for building block layout consisting of rectangular blocks. In contrast to other works, this algorithm enables a router to deal with the channel intersections efficiently, while permitting the expansion of any region when being routed. Before this algorithm is run, it is assumed that proper routing space has been assigned between the circuit blocks, so that the expansion of a region does not greatly affect the general structure. The algorithm starts from the classic set of channels. Each channel is then decomposed into several rectangular regions. If N is the number of channels, there will be around 2N regions at the end of the process. A constraint graph defines the order in which the regions should be routed. Routing results are given to illustrate the efficiency of this new scheme.>

A two-dimensional router utilizing two layers is presented. The routing technique can be described as follows: After partitioning of the nets into a set of subnets, the construction is carried out on a step-by-step basis, which allows the system to dynamically take into account new information. This part has been implemented with a blackboard architecture. The router can handle pins that are not on a grid on one set of parallel edges. To provide a solution to a given problem, the router expands the switch-box by adding rows dynamically where they are needed. Many test cases have been run successfully, and some results, including Burstein's difficult switch-box, are presented.>