Joseph Czarnaski

dblp:92/79 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Energy-efficient computing · 79% Embedded and real-time systems · 21%
Computer networks
1 paper
Internet of things and sensor networks · 100%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing
energy-efficient architecture
0.112005
A modular power-aware microsensor with >1000X dynamic power range · IPSN 2005
Energy-efficient computing
power management
0.112005
A modular power-aware microsensor with >1000X dynamic power range · IPSN 2005
Embedded and real-time systems › real-time embedded systems
hard real-time systems
0.012005
A modular power-aware microsensor with >1000X dynamic power range · IPSN 2005

Methods — techniques the papers use, named apart from their topics

modular architecture design · 0.1sleep mode · 0.1power gating · 0.1duty cycling · 0.1
YearPublicationVenuePosition
2005 A modular power-aware microsensor with >1000X dynamic power range
abstract
We introduce a power-aware microsensor architecture supporting a wide operational power range (from10 W). The platform consists of a family of modules that follow a common set of design principles. Each module includes a local power microcontroller, power switches, and isolation switches to enable independent power-down control of modules and module subsystems. Processing resources are scaled appropriately on each module for their role in the collective system. Hard real-time functions are migrated to the sensor and radio modules for improved power efficiency. The optional Linux-based processor module supports high duty cycling and advanced sleep modes. Our reference hardware implementation is described in detail in this paper. Seven different modules have been developed. We utilize an acoustic vehicle tracking application to demonstrate how the architecture operates and report on results from field tests on tracked and wheeled vehicles.
Brian Schott, Michael Bajura, Joseph Czarnaski, Jaroslav Flidr, Tam Tho
IPSN3
2003 A modular power-aware wireless microsensor architecture
abstract
No abstract available.
Michael Bajura, Brian Schott, Carl D. Worth, Ronald Riley, Joseph Czarnaski
SenSys5
1999 Architectures for System-Level Applications of Adaptive Computing
abstract
The mission of the Systems-Level Applications of Adaptive Computing (SLAAC) project is to design and implement a distributed adaptive computing systems architecture. This systems-level focus of SLAAC resulted from the realization that scalability and portability are the two main obstructions preventing innovative Adaptive Computing Systems (ACS) research from being directly useful in deployed real-time environments. Scalability is an issue in that many real-world applications are larger than the modern PCI-based FPGA accelerator. Transitioning from a small proof of concept demonstration to large real-world application is often overlooked in ACS research. Portability has both a hardware and software aspect. Physical form-factor and operating system issues can limit the utility ACS research done in the lab with desktop PCs unless there is a development path to more traditional real-time environments. The SLAAC project seeks to remedy these issues of scalability and portability in ACS systems.
Brian Schott, Steve Crago, Joseph Czarnaski, Matthew French, Ivan Hom, Tam Tho, Terri Valenti
FCCM4