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James Victory

dblp:92/8972 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 77% Electronic design automation · 12% Performance modeling and evaluation · 12%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › analog and mixed-signal circuits
device modeling
0.112010
Statistical Modeling With the PSP MOSFET Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Integrated circuit design › variation-aware design
variability analysis
0.112010
Statistical Modeling With the PSP MOSFET Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation
circuit simulation
0.012010
Statistical Modeling With the PSP MOSFET Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Performance modeling and evaluation › simulation
monte carlo simulation
0.012010
Statistical Modeling With the PSP MOSFET Model · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010

Methods — techniques the papers use, named apart from their topics

monte carlo simulation · 0.1backward propagation of variance · 0.1
YearPublicationVenuePosition
2010 Statistical Modeling With the PSP MOSFET Model
abstract
PSP and the backward propagation of variance (BPV) method are used to characterize the statistical variations of metal-oxide-semiconductor field effect transistors (MOSFETs). BPV statistical modeling of NMOS and PMOS devices is, for the first time, coupled by including self-consistent modeling of ring oscillator gate delays. Parasitic capacitances are included in the analysis. The proposed technique is validated using Monte-Carlo simulations and by comparison to experimental data from two technologies.
Colin C. McAndrew, Weimin Wu 0004, Samir Chaudhry, James Victory, Gennady Gildenblat
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5