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Shyh-Hao Kuo

dblp:92/9299 · DBLP profile ↗
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7ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 6Security and privacy · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 39% GPUs and heterogeneous computing · 30% Memory systems · 30%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
GPU computing
0.212013
Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes · SC 2013
Memory systems › memory-efficient data structures
sparse matrix compression
0.212013
Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes · SC 2013
High-performance computing › sparse linear algebra › sparse matrix computation
sparse matrix-vector multiplication
0.212013
Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes · SC 2013
High-performance computing
performance optimization
0.012013
Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes · SC 2013

Methods — techniques the papers use, named apart from their topics

matrix reordering · 0.2data clustering · 0.2bit-representation-optimized compression · 0.2
YearPublicationVenuePosition
2013 Optimizing and Auto-Tuning Iterative Stencil Loops for GPUs with the In-Plane Method
abstract
Stencils represent an important class of computations that are used in many scientific disciplines. Increasingly, many of the stencil computations in scientific applications are being offloaded to GPUs to improve running times. Since a large part of the simulation time is spent inside the stencil kernels, optimizing the kernel is therefore important in the context of achieving greater computation efficiencies and reducing simulation time. In this work, we proposed a novel in-plane method for stencil computations on GPUs and compared its performance with the conventional method implemented in the Nvidia SDK. We also implemented an auto-tuning framework for our method to select the optimal parameters for different GPU architectures. A performance model was developed for our proposed method, and is used to speed up the auto-tuning process. Our results show that a speedup of nearly 2× can be achieved compared to Nvidia's implementation.
Wai Teng Tang, Wen Jun Tan, Ratna Krishnamoorthy, Yi Wen Wong, Shyh-Hao Kuo, Rick Siow Mong Goh, Stephen John Turner, Weng-Fai Wong
IPDPS5
2013 Accelerating sparse matrix-vector multiplication on GPUs using bit-representation-optimized schemes
abstract
The sparse matrix-vector (SpMV) multiplication routine is an important building block used in many iterative algorithms for solving scientific and engineering problems. One of the main challenges of SpMV is its memory-boundedness. Although compression has been proposed previously to improve SpMV performance on CPUs, its use has not been demonstrated on the GPU because of the serial nature of many compression and decompression schemes. In this paper, we introduce a family of bit-representation-optimized (BRO) compression schemes for representing sparse matrices on GPUs. The proposed schemes, BRO-ELL, BRO-COO, and BRO-HYB, perform compression on index data and help to speed up SpMV on GPUs through reduction of memory traffic. Furthermore, we formulate a BRO-aware matrix reordering scheme as a data clustering problem and use it to increase compression ratios. With the proposed schemes, experiments show that average speedups of 1.5x compared to ELLPACK and HYB can be achieved for SpMV on GPUs.
Wai Teng Tang, Wen Jun Tan, Rajarshi Ray 0001, Yi Wen Wong, Weiguang Chen, Shyh-Hao Kuo, Rick Siow Mong Goh, Stephen John Turner, Weng-Fai Wong
SC6
2012 Tulipse: A Visualization Framework for User-Guided Parallelization
Yi Wen Wong, Tomasz Dubrownik, Wai Teng Tang, Wen Jun Tan, Rubing Duan, Rick Siow Mong Goh, Shyh-Hao Kuo, Stephen John Turner, Weng-Fai Wong
Euro-Par7
2012 Automatic Refactoring of Legacy Fortran Code to the Array Slicing Notation
abstract
There are many legacy Fortran programs still in use today, especially scientific codes which were written decades ago. Many of these codes use explicit DO-loops in programs that tend to clutter the code and make it harder to understand and maintain. Modern features of the Fortran language, such as the array slicing notation and introduction of commonly used intrinsic functions, go a long way in helping programmers write code that is easier to read and maintain. We introduce a refactoring tool that can help to transform code to make use of the array slicing notation and related intrinsic functions.
Chandrasehar Rajaseharan, Wen Jun Tan, Wai Teng Tang, Stephen John Turner, Shyh-Hao Kuo, Rick Siow Mong Goh, Weng-Fai Wong
ICPADS5
2011 Establishing Hypothesis for Recurrent System Failures from Cluster Log Files
abstract
A goal for the analysis of supercomputer logs is to establish causal relationships among events which reflect significant state changes in the system. Establishing these relationships is at the heart of failure diagnosis. In principle, a log analysis tool could automate many of the manual steps systems administrators must currently use to diagnose system failures. However, supercomputer logs are unstructured, incomplete and contain considerable ambiguity so that direct discovery of causal relationships is difficult. This paper describes the second generation FDiag log-based failure diagnostics framework that provides automation of the manual failure diagnosis process and determines with high confidence, the likely cause of the failure, the components involved and the event sequences which contain the times of the causal and terminal events. FDiag extracts relevant events from the system logs, performs correlation analysis on these events and from these correlations determines the components involved and the event sequences. The diagnostics capabilities of FDiag are validated by comparing its assessments on known instances of recurrent failures on the Ranger supercomputer at the University of Texas at Austin. We believe FDiag is the first log analyzer to demonstrate this level of diagnostics capability from the system logs of an open source software stack incorporating Linux and the Lustre file system. FDiag will be put into production use for support of failure diagnosis on Ranger in September, 2011.
Edward Chuah, Gary Kee Khoon Lee, William-Chandra Tjhi, Shyh-Hao Kuo, Terence Hung, John L. Hammond, Tommy Minyard, James C. Browne
DASC4
2010 Diagnosing the root-causes of failures from cluster log files
abstract
System event logs are often the primary source of information for diagnosing (and predicting) the causes of failures for cluster systems. Due to interactions among the system hardware and software components, the system event logs for large cluster systems are comprised of streams of interleaved events, and only a small fraction of the events over a small time span are relevant to the diagnosis of a given failure. Furthermore, the process of troubleshooting the causes of failures is largely manual and ad-hoc. In this paper, we present a systematic methodology for reconstructing event order and establishing correlations among events which indicate the root-causes of a given failure from very large syslogs. We developed a diagnostics tool, FDiag, to extract the log entries as structured message templates and uses statistical correlation analysis to establish probable cause and effect relationships for the fault being analyzed. We applied FDiag to analyze failures due to breakdowns in interactions between the Lustre file system and its clients on the Ranger supercomputer at the Texas Advanced Computing Center (TACC). The results are positive. FDiag is able to identify the dates and the time periods that contain the significant events which eventually led to the occurrence of compute node soft lockups.
Edward Chuah, Shyh-Hao Kuo, Paul Hiew, William-Chandra Tjhi, Gary Kee Khoon Lee, John L. Hammond, Marek T. Michalewicz, Terence Hung, James C. Browne
HiPC2
2009 A Tabu Search for the Heterogeneous DAG Scheduling Problem
abstract
Scheduling parallel applications on heterogeneous processors/architectures with different computational speed is a difficult problem. Here, a tabu search metaheuristic is developed to improve the schedule generated by list scheduling. Three neighbourhoods variants are proposed and examined, including a novel neighbourhood that takes the shape of the task graph into account. The effectiveness is evaluated based on a set of modified random benchmark graphs, including task graphs of real-world applications. Factors affecting algorithm performance are also examined. We have found that the variants proposed were able to reduce the schedule length produced by HEFT up to an average of 30% and up to on average 20% for the standard graphs. The results also show that using information about the shape of the task graph is a viable strategy.
Yi Wen Wong, Rick Siow Mong Goh, Shyh-Hao Kuo, Malcolm Y. H. Low
ICPADS3