This paper presents a digital-to-analog converter (DAC) sharing method for time-interleaved (TI)-incremental delta-sigma modulators (I-ΔΣMs), which allows significant savings of passives by 40 % in the DACs. The proposed DAC sharing shows an increased robustness to nonlinearities and is further adapted to a linearization technique known from non-TI-I-ΔΣMs. The paper extends the known linearization technique to achieve optimal signal to noise and distortion ratio (SNDR) across the modulator’s entire dynamic range (DR). An increase of 7 dB in SNDR is demonstrated for low input signals powers, which has not been shown before. It is demonstrated, that the high linearity of the system allows to compensate for the gain mismatch in TI operation with a simple gain factor to retain near ideal performance. Furthermore, the paper proposes a practical circuit implementation for the shared DAC and a correlation based error estimation to determine the channel gain mismatch.

This paper presents a new architecture as well as a compensation method for discrete-time (DT) noise-canceling SMASH (NC-SMASH) bandpass delta-sigma modula-tors$(\mathbf{BP}-\Delta\Sigma \mathbf{Ms})$. The proposed method relaxes timing constraints on the feedback path by one clock cycle, which in turn relaxes the timing constraints on the adder in front of the quantizer, and the digital adder for the SMASH architecture. In SMASH architectures, this relaxed timing enables an NC analog-to-digital converter (ADC) architecture. Unlike state-of-the-art solutions, which require an analog unit delay at the ADC's input to achieve these relaxed requirements, the presented bandpass approach renders this analog delay and the respective input capacitor unnecessary. In a respective circuit implementation this significantly reduces the area and power consumption. The proposed compensation method allows the designer to choose between a non-delayed input and an elimination of the input signal component inside the loop filter, which would require a delayed input path.

In this paper we present a correlation based error estimation technique using a residual test signal for the linearization of multibit feedback DACs of lowpass and bandpass Delta-Sigma analog-to-digital converters. Using residual test signal insertion allows operating in background with only limited loss in peak performance during test. Opposed to dynamic element matching techniques, which are limited by the intrinsic nonlinearities in the feedback DAC, the presented method recovers the performance of highly nonlinear systems back to their ideal resolution.

This paper presents different alternatives for a hardware realization of a previously proposed correlation based background error estimation and correction technique. The technique is used to linearize the unit elements in the feedback DAC of a ΔΣ analog-to-digital converter (ΔΣ ADC). General system simplifications to reduce the necessary hardware are presented and verified by simulations. The hardware needed to realize key parts of the method-with the simplifications included-is compared between the different implementation alternatives. The hardware comparison is done for gate level implementations of an exemplary modulator, which is combined with the background estimation and correction system. Finally, the most suitable structure for an implementation is identified.

This paper presents a new approach for estimating nonidealities in unit element feedback digital-to-analog converters (DACs) of sigma-delta analog-to-digital converters (SigmaDelta ADCs). The presented method involves a background correlation technique to determine static and dynamic device mismatches as well as a way to digitally correct a modulators output. Simulations show that the method can be used to precisely estimate imperfections and improve non-ideal modulators up to their ideal resolution. The method is defined mathematically and verified by simulations.