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Shaoxia Fang

dblp:93/10799 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorComputer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Artificial intelligence
1 paper
Efficient and distributed learning · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator
CNN accelerator
0.412020
LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020
Hardware accelerators and domain-specific architectures › machine learning accelerator › CNN accelerator
FPGA-based CNN accelerator
0.412020
LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020
Hardware accelerators and domain-specific architectures › machine learning accelerator
low-bit quantization accelerator
0.412020
LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020
Machine learning › Efficient and distributed learning
model compression
0.112020
LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020
Machine learning › Efficient and distributed learning › model compression
quantization
0.112020
LPAC: A Low-Precision Accelerator for CNN on FPGAs · FPGA 2020

Methods — techniques the papers use, named apart from their topics

DSP mapping · 0.94a4w quantization · 0.9
YearPublicationVenuePosition
2020 LPAC: A Low-Precision Accelerator for CNN on FPGAs
abstract
Low bit quantization of neural network is required on edge devices to achieve lower power consumption and higher performance. 8bit or binary network either consumes a lot of resources or has accuracy degradation. Thus, a full-process hardware-friendly quantization solution of 4A4W (activations 4bit and weights 4bit) is proposed to achieve better accuracy/resource trade-off. It doesn't contain any additional floating operations and achieve accuracy comparable to full-precision. We also implement a low-precision accelerator for CNN (LPAC) on the Xilinx FPGA, which takes full advantage of its DSP by efficiently mapping convolutional computations. Through on-chip reassign management and resource-saving analysis, high performance can be achieved on small chips. Our 4A4W solution achieves 1.8x higher performance than 8A8W and 2.42x increase in power efficiency under the same resource. On ImageNet classification, the accuracy has a gap less than 1% to full-precision in Top-5. On the human pose estimation, we achieve 261 frames per second on ZU2EG, which is 1.78x speed up compared to 8A8W and the accuracy has only 1.62% gap to full-precision. This proves that our solution has better universality.
Tiantian Han, Xijie Jia, Guangdong Liu, Pingbo An, Yingran Tan, Lingzhi Sui, Shaoxia Fang, Dongliang Xie, Michaela Blott
FPGA10
2018 Real-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning Networks
abstract
Advanced Driver Assistance Systems (ADAS) help the driver in the driving process by detecting objects, doing basic classification, implementing safety guards and so on. Convolution Neural Networks (CNN) has been proved to be an essential to support ADAS. We designed an architecture named Aristotle to execute neural networks for both object detection and semantic segmentation on FPGA. DNNDK (Deep Learning Development Toolkit), a full-stack software tool, with tens of compilation optimization techniques is proposed to improve the energy efficiency and make it easy to develop. The Aristotle architecture is implemented on Xilinx ZU9 FPGA, and two networks are deployed on it to execute object detection and semantic segmentation, respectively.
Shaoxia Fang, Shuang Liang 0010, Dongliang Xie, Zhongmin Chen, Lingzhi Sui, Yu Wang 0002
FPT1
2011 A Heterogeneous High Speed Wireless Body Sensor Network Based on SC-UWB and ZIGBEE
abstract
Some new medical applications, such as wireless endoscopy system for the diagnoses of whole human digestive tract and real-time endoscopic image monitoring, demand high speed transmission in wireless body sensor network (WBSN). This paper proposes a heterogeneous high speed wireless body sensor network based on ZIGBEE and single carrier ultra wideband (SC-UWB). Our system can choose high speed mode or low speed mode automatically according to the type of data source. Several measures are taken to miniaturize the nodes, lower the system complexity and reduce power consumption, offering system users great mobility and flexibility. We develop and validate a prototype WBSN, supporting four real-time high speed video streams and six low speed sensor data. The performance of the developed system is experimentally evaluated using prototype WBSN, and the ASIC has been designed and fabricated in the standard 0.18im CMOS technology, occupying a die area of 3.0mm * 3.0mm and consuming a dynamic power of 43.4280mw.
Xinlei Chen, Xiyu Lu, Zhongjin Liu, Shaoxia Fang, Depeng Jin, Lieguang Zeng
GLOBECOM4