Coarse-Grained Reconfigurable Architecture (CGRA) in a hybrid system can significantly accelerate the execution of compute-intensive kernels of applications. However, the data communication overhead between the main processor (MP) and the CGRA may be huge and can negate the speed-up of the CGRA. In this paper we address the problem of reducing the data communication overhead in a hybrid system by offering a partially automatic data sharing technique using a special shared memory called Configurable Range Memory (CRM). Unlike the previous work the CRM architecture we use here is based on comparators, which gives much higher flexibility in terms of where an array can be placed within a CRM while it makes the runtime software management of a CRM much more challenging. We present an efficient runtime algorithm based on first-fit heuristic. Our experimental results demonstrate that our CRM-based system can reduce the amount of data transfer between a MP and a CGRA up to 89.5% compared to ScratchPad Memory (SPM)-based systems, while the software management overhead is only 1.20~1.34% on average (depending on CRM architecture parameters) of the kernel cycles in the MP-only execution. Overall our CRM-based system can achieve average kernel speedup of 3.47 times over the MP-only execution, which is about 20% improvement over the SPM-based system.

Pipelining algorithms are typically concerned with improving only the steady-state performance, or the kernel time. The pipeline setup time happens only once and therefore can be negligible compared to the kernel time. However, for Coarse-Grained Reconfigurable Architectures (CGRAs) used as a coprocessor to a main processor, pipeline setup can take much longer due to the communication delay between the two processors, and can become significant if it is repeated in an outer loop of a loop nest. In this paper we evaluate the overhead of such non-kernel execution times when mapping nested loops for CGRAs, and propose a novel architecture-compiler cooperative scheme to reduce the overhead, while also minimizing the number of extra configurations required. Our experimental results using loops from multimedia and scientific domains demonstrate that our proposed techniques can greatly increase the performance of nested loops by up to 2.87 times compared to the conventional approach of accelerating only the innermost loops. Moreover, the mappings generated by our techniques require only a modest number of configurations that can fit in recent reconfigurable architectures.