This article presents analytical tools for high-level design of the leapfrog (LF) control-bounded analog-to-digital converter (CBADC). We derive closed-form design equations for parameterizing the analog system for a target signal-to-noise ratio (SNR) and bandwidth. Furthermore, we show how the parameterization can be modified to compensate for finite amplifier gain-bandwidth product (GBWP) and to control the signal swing at different nodes of the system. Behavioral circuit simulations are used to compare the LF CBADC to relevant continuous-time sigma–delta modulators (CT-$\Sigma \Delta $Ms) in terms of nominal performance and sensitivity to component variations, clock jitter, and finite GBWP. Simulations show that the nominal performance of the LF is similar to that of a CT-$\Sigma \Delta \text{M}$of the same loop-filter order and with the same number of quantization levels. The simple, modular structure, analytical stability guarantee, and single-bit quantizers make the LF an interesting alternative to conventional CT-$\Sigma \Delta $Ms.

This paper presents a differential Power Amplifier (PA) for operation in the D-band. The simulated PA has gain of 8 dB/stage at 160 GHz for a total gain of 32 dB, a saturated output power of 11 dBm, a peak power added efficiency (PAE) of 9.8%, and a 3-dB bandwidth of 7 GHz. The PA consumes a power of 112 mW from 1.1 V supply. The PA core area is 0.052 mm 2 in 28-nm FD-SOI technology.

Oversampling and noise-shaping have in recent years been introduced to SAR ADCs to improve the conversion accuracy. Similar to delta-sigma ADCs, this is done by means of a feedback loop containing a loop filter. In this paper, the high-level design of this loop filter is discussed, and important differences to classical delta-sigma loop filter design are pointed out. Among others, it is found that the poles of the noise transfer function, and not only the zeros, play a significant role on the conversion accuracy. Based on this, a new loop filter topology with four poles and two zeros is proposed and compared to existing loop filters. This reveals that the proposed loop filter can yield more energy-efficient noise-shaping SAR ADCs than the ones seen in the literature today.

As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The conditionVsb> 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, asVsb> 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.