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Jong Mun Park

dblp:93/1420 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2005
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
mesh generation
0.112005
A method for generating structurally aligned grids for semiconductor device simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Electronic design automation › technology computer-aided design
semiconductor device simulation
0.112005
A method for generating structurally aligned grids for semiconductor device simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Integrated circuit design
semiconductor device modeling
0.012005
A method for generating structurally aligned grids for semiconductor device simulation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005

Methods — techniques the papers use, named apart from their topics

level set method · 0.1
YearPublicationVenuePosition
2005 A method for generating structurally aligned grids for semiconductor device simulation
abstract
The quality of the numeric approximation of the partial differential equations governing carrier transport in semiconductor devices depends particularly on the grid. The method of choice is to use structurally aligned grids since the regions and directions therein that determine device behavior are usually straightforward to find as they depend on the distribution of doping. Here, the authors present an algorithm for generating structurally aligned grids including anisotropy with resolutions varying over several orders of magnitude. The algorithm is based on a level set approach and permits to define the refined resolutions in a flexible manner as a function of doping. Furthermore, criteria on grid quality can be enforced. In order to show the practicability of this method, the authors study the examples of a trench gate metal-oxide-semiconductor field-effect transistor (TMOSFET) and a radio frequency silicon-on-insulator lateral double diffused metal-oxide-semiconductor (RF SOI LDMOS) power device using the device simulator MINIMOS NT, where simulations are performed on a grid generated by the new algorithm. In order to resolve the interesting regions of the TMOSFET and the RF SOI LDMOS power device accurately, several regions of refinement were defined where the grid was grown with varying resolutions.
Clemens Heitzinger, Alireza Sheikholeslami, Jong Mun Park, Siegfried Selberherr
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3