The memory-based hippocampus-inspired model (MBHIM) that has been proposed by the authors is a model that reproduces episodic memory suitable for VLSI implementation. While an MBHIM VLSI circuit can achieve high energy efficiency using the in-memory computing architecture with thermometer coding, its computational functionality was limited to addition operation. The use of thermometer coding, though enabling simple VLSI implementation, remains an integration density challenge. In this paper, we propose a memory cell circuit for MBHIM, which supports addition and subtraction using in-memory computing, enabling broader applications, including time-dependent forgetting mechanisms. We also propose a carry-over thermometer coding scheme for efficient value representation, achieving a reduction of 60-90% transistor count compared to conventional approaches. This scheme maintains the advantages of thermometer coding while achieving high integration density, making it particularly effective for memory devices with high write error rates, such as MRAM and ReRAM. The proposed scheme is promising for realizing brain-inspired AI hardware that achieves low power consumption, high computational efficiency, and high integration density.

Deep neural networks (DNNs) have enabled state-of-the-art performance across various applications. However, their deployment is often hindered by high energy demands. One solution is to deploy DNNs on hardware equipped with emerging non-volatile memory, which does not require energy to maintain memory state. Nonetheless, this approach may introduce bit-flips in DNN parameters, leading to a drop in model performance. To mitigate this issue, ternary neural networks (TNNs), which are known for their robustness against bit-flips, can be utilized. To accelerate TNNs, it is necessary to define binary representations (BRs) for ternary values to enable bit-wise operations. This paper proposes a framework for identifying a set of BRs that minimizes the discrepancy between the Top-1 Accuracy of TNNs before and after bit-flips, thereby enhancing their robustness. The BRs are evaluated using randomly generated data, the CIFAR-10 dataset, and the ImageNet 2012 dataset. The experimental results demonstrate that our BRs can significantly reduce or maintain the Top-1 Accuracy degradation caused by bit-flips, compared to conventional BRs.

Home service robots acquire environment-specific knowledge through experiences (episodes) in a home to perform tasks autonomously. We propose a hippocampus-inspired memory system comprising an environment-specific knowledge module that handles episodic memory and a common knowledge module. The robot works in a home and needs to learn the locations of objects in the home with minimal user help to deliver or store objects. We employ a large language model (LLM) that runs on an edge device as the common knowledge module to protect the privacy of users. The environment-specific knowledge module acquires episodes and generates contextual information. The LLM receives contextual information generated by the environment-specific knowledge module, with which it infers an appropriate possible location. We verified that the LLM could infer the possible object locations and that the proposed system could minimize the required user effort.

For artificial intelligence (AI) to be useful in the home, it is required to acquire unique knowledge of the home obtained through interaction with space and environment. This is difficult for deep learning-based AI. The human brain can learn unique knowledge from few experiences. The entorhinal cortex and hippocampus play essential roles for episodic memory formation and recall. While entorhinal-hippocampal models have been proposed that can reproduce episodic memory, hardware systems that implement such models face challenges related to high computational complexity, power consumption, and processing speed. In this paper, we propose a digital-analog mixed-signal CMOS VLSI implementation of a hippocampus-inspired model that can memorize and associate place and object information essential for the formation of episodic memory. By using both analog and digital in-memory computing architecture, the proposed circuit has achieved a computational efficiency of 22 TOPS/W, which is very high for AI hardware with a learning function. The proposed circuit was fabricated, measured, and evaluated. The results of an experiment using a fabricated chip and a control system showed that the proposed circuit can memorize and process place and object information, and can acquire environment-unique knowledge through interaction with a space.

To use reservoir computing (RC) for practical tasks, both a high memory capacity and nonlinearity are required; however, some RC models have the problem of a low memory capacity. We propose a delay mechanism for increasing the memory capacity in RC as well as a simple and small-scale digital circuit for implementing the delay mechanism. The proposed delay mechanism is integrated into the input layer of the RC model and is expected to be implemented in several RC models, such as material reservoirs and chaotic Boltzmann machine (CBM)-RC. We conducted experiments using a CBM-RC with a delay mechanism (CBM-RC-DL) and evaluated the performance improvement achieved by introducing a delay mechanism. We used CBM-RC as the base model because it is an appropriate model for the hardware implementation of large networks but has a low memory capacity. The experimental results for CBM-RC-DL indicated that the delay mechanism significantly increased the memory capacity of CBM-RC with the addition of a small-scale circuit. Furthermore, the entire synthesized CBM-RC-DL was sufficiently small-scale to be implemented in a field-programmable gate array for edge computing, and it outperformed conventional methods in nonlinear autoregressive moving average 10 (NARMA10)—a benchmark task for time-series data processing. The proposed delay mechanism can facilitate the use of many RC models because of its simple structure.

Emerging non-volatile memory devices, such as resistive random access memory (ReRAM) and voltage-controlled magnetoresistive random access memory (VC-MRAM), promise low energy consumption for artificial intelligence applications. However, when implementing deep neural networks (DNNs) using such memory devices, write-error may cause millions of bit-flipping to DNN. This easily degrades the DNN performance. To address this problem, we propose a novel repetition coding for deep-learning (RC-DL), which is a repetition coding designed to protect IEEE 32-bit floating-point (FP32) DNN models. Compared to conventional repetition coding, the proposed RC-DL exploits FP32 non-uniform magnitude encoding by increasing the repeat rates to protect sensitive bit positions and reduce the repeat rates to insensitive bit positions. Hence, RC-DL uses a number of bits equivalent to a 3-bit repetition code while delivering the performance close to 11-bit repetition code. We perform extensive Monte Carlo simulations to simulate the write-error property with ImageNet 2012 pretrained models. The DNN models with RC-DL are shown to be operable in the extremely imperfect environment while delivering with only minor reductions in DNN performance.

Ising machines are attracting attention for their ability to solve large-scale combinatorial optimization problems because these problems are difficult to solve. To accelerate the computing of Ising machines, implementation of Ising machines with digital circuits such as simulated annealing (SA) machines is in progress. However, these Ising machines on digital circuits require random number generators, which are implemented with large circuit resources. This work focuses on chaotic Boltzmann machines (CBMs), which imitate the stochastic behavior of Boltzmann machines (BMs) with deterministic chaotic dynamics. CBMs are one of the models that work as chaotic simulated annealing (CSA) machines within Ising machines. Therefore, we can implement the Ising machines without random number generators by using CBMs. In conventional work, CSA machines using CBMs (CBM-CSAs) are implemented with some hardware-oriented algorithms, but the CBM-CSA circuit is not optimized for these hardware-oriented algorithms. In the conventional CBM-CSA circuit, memory circuits are implemented separately, which prevents making the CBM-CSA from larger, and neuron circuits require the reset of accumulated values, which causes the increase in the calculation time. To solve these problems, we implement only one large memory circuit to make the CBM-CSA larger and improve the neuron circuits to allow dynamic changes of inputs to arithmetic circuits to inhibit the increase in the calculation time. As a result, we implement a CBM-CSA with 4096 nodes on an FPGA (Alveo U250), and the CBM-CSA can control 16-bit width weights and run at 100MHz. We evaluate the implemented CBM-CSA by solving K4000, max-cut problem, which is one of the combinatorial optimization problems. The best solution of CBM-CSA is comparable to that of the SA on the central processing unit (CPU). Moreover, the CBM-CSA is approximately 600 times as fast as the SA on the CPU and approximately twice as fast as the conventional Ising machine on an FPGA based on the improvements in this work. Furthermore, this work implements one of the highest-performance Ising machines on a single FPGA.

Spiking neural networks (SNNs) are brain-inspired mathematical models with the ability to process information in the form of spikes. SNNs are expected to provide not only new machine-learning algorithms but also energy-efficient computational models when implemented in very-large-scale integration (VLSI) circuits. In this article, we propose a novel supervised learning algorithm for SNNs based on temporal coding. A spiking neuron in this algorithm is designed to facilitate analog VLSI implementations with analog resistive memory, by which ultrahigh energy efficiency can be achieved. We also propose several techniques to improve the performance on recognition tasks and show that the classification accuracy of the proposed algorithm is as high as that of the state-of-the-art temporal coding SNN algorithms on the MNIST and Fashion-MNIST datasets. Finally, we discuss the robustness of the proposed SNNs against variations that arise from the device manufacturing process and are unavoidable in analog VLSI implementation. We also propose a technique to suppress the effects of variations in the manufacturing process on the recognition performance.

Artificial general intelligence, which imitates the human brain, is aspired. Episodic memories are considered to be a key feature in building human brain functions. This paper proposes a memory-based entorhinal-hippocampal model that encodes spatial and non-spatial information, essential to realize episodic memories. The model works as a memory that stores the location of objects and events as neural activity packets. This paper also proposes an area-efficient hardware implementation method for field-programmable gate arrays (FPGAs). Our proposal utilizes on-chip random access memories (RAMs) to achieve a large-scale implementation of our model. Circuit simulations validated the behavior of our hardware-friendly model. The results of logic synthesis revealed the area efficiency of the FPGA implementation method that utilizes on-chip RAMs.

Spiking neural networks (SNNs) are expected to be energy efficient when implemented on dedicated hardware. However, fully exploiting SNN’s characteristics such as event-driven communications challenges on circuit designers and manufacturers. In this paper, inspired by the recent success of an artificial neural network (ANN) based system, known as charge-domain computing (CDC), we propose a novel framework for SNNs called “RC-Spike.” As CDC, RC-Spike uses a two-phase system: input spikes are received in the accumulation phase, and a neuron produces a spike in the spike generation phase. In RC-Spike, synaptic currents are accumulated with resistively coupled synapses, with which circuit implementation can be simplified compared with CDC circuits. Because of this resistive coupling effect, a neuron in RC-Spike does not compute an exact dot product. However, RC-Spike can be successfully trained in the framework of SNNs, and we show that the learning performance of RC-Spike is as high as ANNs on the MNIST and Fashion-MNIST datasets.

In our work, a new area-efficient multiply-accumulation scheme for time-domain neural processing named differential multiply-accumulation is proposed. Our new scheme reduces hardware resources utilization of multiply-accumulation with suppressing the increasing computational time resulting from the time-multiplexing. As a result, 2,048 neurons of fully connected CBM and RC-CBM were synthesized for a single field-programmable gate array (FPGA).

Reservoir computing (RC) is a framework for constructing recurrent neural networks with simple training rule and sparsely and randomly connected nonlinear units. The network (called reservoir) generates complex motion that can be used for many tasks including time series generation and prediction. We construct a reservoir based on the dynamics of the pseudo-billiard system that produce complex motion in a high-dimensional hypercube. In particular, we use the chaotic Boltzmann machine (CBM) whose units exhibit chaotic behavior in the hypercube. The units interact with each other in a time-domain manner through its binary state, and thus an efficient hardware implementation of the system is expected. In order to utilize the CBM as the reservoir, it is necessary to control its chaotic behavior for ensuring the echo state property of RC and establish encoding and decoding for input and output signal. For this purpose, we introduce a reference clock and analyze effects and properties of the reference input. We evaluate the proposed model on the time series generation tasks and show that the model works properly on a broad range of parameter values. Our approach presents a novel mechanism for time-domain information processing and a fundamental technology for a brain like artificial intelligence system.

Reservoir computing is attracting great interest because of its high computing ability especially for time-series prediction, despite its simple structure and learning scheme. This paper proposes a reservoir computing hardware model using a chaotic Boltzmann machine (CBM) as the reservoir, which can achieve complex motion in a dynamical system on a high-dimensional hypercube. The CBM uses analog nonlinear dynamics, unlike the stochastic operation of the original Boltzmann machine model. To utilize CBMs as a reservoir, chaotic operation must be suppressed, and the echo state property should be satisfied. We modify the CBM model for simpler analog complementary metal-oxide-semiconductor very-large-scale integration (CMOS VLSI) implementation, and propose its use as a reservoir by adding an external reference clock signal. We then verify its proper operation by numerical simulation. We also refine the CMOS VLSI circuit design based on the proposed modified CBM model to improve power consumption and calculation precision.

This live demonstration presents a VLSI chip based on “Time-domain Analog Computing with Transient states (TACT)” approach for intelligent processing on robots. This TACT chip, fabricated using 250-nm CMOS technology, implements a time-domain analog weighted-sum calculation model with very high energy efficiency. We integrate the TACT chip into a robot via Robot Operating System (ROS) interfaces. A human tracking robot demonstration is performed by the TACT chip with energy efficiency of 300 TOPS/W.

This live demonstration presents a "connective object for middleware to accelerator (COMTA)," an intelligent processing system that uses hardware accelerators (i.e., field programmable gate arrays (FPGAs)) and robot middleware. The key idea of COMTA is to automatically generate the system via robot middleware interfaces. To realize the proposed system, we have developed a block of programs called an "object" in a hardware/software complex system. We demonstrate an implementation of a human tracking image processing application on a vehicle robot accelerated by COMTA. The demonstration system achieved 3.3 times better power efficiency than a general PCs.

Service robots require implementation of intelligent processing, e.g., image processing. However, the computational resources of standard PCs typically used in service robots are not sufficient for such processes. Furthermore, robot middleware is widely used in many robots because such systems facilitate integration and are suitable for rapid prototyping. We propose a "connective object for middleware to accelerator (COMTA)," which is a processing system that uses hardware accelerators, i.e., field programmable gate arrays (FPGAs), and robot middleware. Users can access the FPGAs in the proposed system via middleware interfaces; thus, complex internal circuits are not required. For human tracking using image processing, the proposed system can automatically generate from a single configuration file. The proposed system performs 3.3 times more efficiently relative to computation than standard PCs in robots.

This paper proposes CMOS VLSI implementation of a chaotic Boltzmann machine (CBM) model, which uses analog nonlinear dynamics instead of stochastic operation as in the original Boltzmann machine model. The CBM model is suitable for efficient VLSI implementation of Boltzmann machines because it requires no random number generator circuits, which consume a considerable footprint on a VLSI chip as well as considerable power. We describe the design results of CMOS circuits of neuron and synapse units. The neuron circuit uses subthreshold operation of MOSFETs to realize the exponential function used in the CBM model. We also provide measurement results of a fabricated CMOS chip for single-neuron unit circuit operation and demonstrate chaotic behavior in a three-neuron network.

In the implementation of spiking neuron models, which can achieve realistic neuron operation, generation of post-synaptic potentials (PSPs) is an essential function. We have already proposed a new nanodisk array structure for generating PSPs using delay in electron hopping among nanodisks. Generated PSPs have fluctuation caused by stochastic electron movement. Noise or fluctuation is effectively used in neural processing. In this paper, we review our proposed structure and show fluctuation controllability based on single-electron circuit simulation.

In this paper, we propose analog CMOS circuit implementation of a system of coupled phase oscillators with pulse coupling for spiking neural networks. We have designed and fabricated a CMOS circuit that achieves the dynamics of pulse coupled oscillators using TSMC 0.25-μm CMOS technology. In our circuit, oscillator circuits with continuous-time operation interact with each other via a pulse at each firing time. We demonstrate experimentally that the circuit exhibits in- and anti phase as well as out-of-phase synchronization. Such properties are essential for spike-based computation in neuromorphic systems.

Spiking neuron models, which simplify the biological neuron function, have attracted much attention recently in the fields of computational neuroscience and artificial neural networks. In these models, generation of post-synaptic potentials (PSPs) is an essential function. In this paper, we propose a new nanodevice structure using a nanodisk array connected to a MOSFET for spiking neuron models. The structure generates PSPs by taking advantage of the delay in electron hopping movement among nanodisks. The results of single-electron circuit simulation demonstrate the controllability of PSP shapes by a control gate placed over the nanodisk array.

In system LSIs, costs of analog circuits are getting increased relatively for rapid cost reduction of digital circuits. To satisfy given specifications in the analog design, including low power and small area, designers have to select an optimal solution among large combination of the following alternatives: which architecture should be adopted; what type of transistors should be taken; and whether digitally assisting technologies should be used or not, etc. A design based on experience and intuition cannot lead to the optimum in a short time. A comprehensive approach to the optimization, based on circuit theory, is now required. Convex optimization procedure can solve the formulae which represent circuit performance with over hundreds of design variables. We have constructed optimization environments for pipelined and delta-sigma analog-to-digital converters (ADCs) in consideration of the digitally assisting techniques and layout constraints. Both 12-bit pipelined ADCs and a 5th-order delta-sigma modulator were designed with the optimizer, and achieved top-ranked power efficiency.

This paper proposes a novel region-based coupled Markov random field (MRF) model for coarse image region segmentation on silicon platforms. Coupled MRF models are classified into boundary- and region-based models, in which hidden variables are referred to as a line process and a label process, respectively. These hidden variables are crucial for detecting discontinuities in motion, intensity, color, and depth in visual scenes. For a coarse image region segmentation task, we address a region-based coupled MRF model with hidden phase variables. It is shown that the region-based coupled MRF model has an advantage over the resistive-fuse network, which is a boundary-based coupled MRF model, in dealing with the hidden variables explicitly. These models work complementarily for a coarse image region segmentation task. For real-time region segmentation operation, we have designed a merged analog/digital CMOS circuit implementing both functions of the boundary- and region-based coupled MRF models using a pulse modulation approach.

We propose a method for detecting precursors, such as small rock and/or soil fall, which occur prior to massive slope failure. The key feature of our method is directly recognizing the trajectory of a small collapse using spatiotemporal Gabor filtering. Simulation analysis, where the conditions of the simulation are quantitatively defined, reveals the effectiveness of the proposed method in detecting a tiny moving object with low contrast in the background under low frame-rate video monitoring. Experiments using actual monitoring videos of a hazardous slope confirmed the effectiveness of our method. The effects of error factors in an outdoor environment, which may inhibit recognition, are also evaluated.

In this paper, we have applied the pulse-modulation circuit technique to implement phase-locked loop (PLL) neural networks proposed by Hoppensteadt and Izhikevich. The PLL neural network is an oscillatory neural network as a model of associative memory, and it is represented as coupled phase oscillators with periodic phase variables and periodic nonlinear interactions. In our circuit implementation, the phase variables and their summation and subtraction are represented by pulse-width modulation (PWM) signals. The interactions are realized by using nonlinear current waveform sampled with pulse-phase modulation (PPM) signals converted from the PWM signals. We have designed an element circuit and simulated two coupled such circuits with SPICE using the TSMC 0.25 μm device parameters. The results demonstrate that the element circuits synchronized with in- and anti-phase depending on coupling strength at different operation frequencies. The element circuit has an advantage in extracting phase difference between the circuits. This will facilitate implementing of learning by arbitrary spike-timing dependent plasticity (STDP) rules using the phase difference.

In this paper, we present a user identification technique based on face recognition for secure human-machine interaction. User's face is matched with the faces memorized by the machine, and if a match is found with a reliable matching score, the machine gets ready to accept the commands. Gabor Wavelet Transform coefficients are used as features for matching, and they are computed on a dedicated LSI to attain high computational speed. For matching, an algorithm based on the elastic graph matching is used, and that is also implemented on hardware. We also propose an arm tracking algorithm for communication with machines using arm gesture. The algorithm utilizes stereo vision to define search regions in left and right images iteratively, and looks for the arm posture by matching with a three dimensional four degrees-of-freedom kinematics-based arm model. Tracking procedure is computationally efficient, robust to small occlusions, and works in unconstrained environment, which makes it suitable for general applications in human-machine interaction.

In this paper, we propose an FPGA-based collision warning system for advanced automobile driver assistance systems or autonomous moving robots. The system consists of three function blocks: coarse edge detection using a resistive-fuse network, moving-object detection inspired by neuronal propagation in the hippocampus, and danger evaluation and collision warning using fuzzy inference. The first two functions are implemented in FPGAs. The system can detect moving objects with a speed range of 3-192 km/h with a sampling period of 30 ms for an input image of 320 x 256 pixels, and can output a warning against dangerous regions in the input image.

The elastic graph matching (EGM) is known as an excellent algorithm in applications of human face recognition. This paper proposes a digital LSI architecture for EGM and a face/object recognition system using its FPGA implementation. In the EGM, the matching evaluation point graph is distorted to find the best trade-off between better matching in the feature space and less distortion of the evaluation point graph. In the proposed architecture, cache memory stores calculation results at the evaluation points and those at their neighboring pixels to reduce the calculation amount. In the FPGA implementation with a system clock of 48 MHz, EGM between the input and one memorized image can be performed in about 1 ms.

A Transition Controllable Noise Source (TCNS) generates substrate noises with controlled transitions in size, interstage delay, and direction. The noises are measured in a 100-ps 100-uV resolution by a linear substrate voltage detector that uses a front-end PMOS source follower probing substrate potential and a back-end latch comparator for sampling/digitizing the source follower output. A 0.4-um CMOS test chip demonstrates the effectiveness of these circuits in performing advanced researches on the substrate noise.

This paper describes a clustering algorithm for vector quantizers using a “stochastic association model”. It offers a new simple and powerful soft- max adaptation rule. The adaptation process is the same as the on-line K-means clustering method except for adding random fluctuation in the distortion error evaluation process. Simulation results demonstrate that the new algorithm can achieve efficient adaptation as high as the “neural gas” algorithm, which is reported as one of the most efficient clustering methods. It is a key to add uncorrelated random fluctuation in the simi- larity evaluation process for each reference vector. For hardware imple- mentation of this process, we propose a nanostructure, whose operation is described by a single-electron circuit. It positively uses fluctuation in quantum mechanical tunneling processes.

No abstract available.

No abstract available.

Analog-digital merged circuit architecture using pulse modulation signals and its application to functional image sensors with parallel focal plane processing are reported. The architecture is based on switched current integration and time domain charge-to-pulse conversion techniques. Parallel analog calculations such as add/sub and multiply/add are realized with low supply voltage and low power dissipation utilizing deep-sub /spl mu/m CMOS technologies. A functional CMOS image sensor which realizes parallel PWM readout, block averaging for gray scale image data, and simple pattern detection, and calculations for x- and y-projections and centers of gravity of binary image data, is proposed. A functional image sensor test chip with 56/spl times/56 pixels was fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology is described.

A transition-controllable noise source is developed in a 0.1-/spl mu/m P-substrate N-well CMOS technology. This noise source can generate substrate noises with controlled transitions in size, interstage delay and direction for experimental studies on substrate noise properties in a mixed-signal integrated circuit environment. Substrate noise measurements of 100 ps, 100-/spl mu/s resolution are performed by indirect sensing that uses the threshold voltage shift in a latch comparator and by direct probing that uses a PMOS source follower. Measured waveforms indicate that peaks reflecting logic transition frequencies have a time constant that is more than ten times larger than the switching time. Analyses with equivalent circuits confirm that charge transfer between the entire parasitic capacitance in digital circuits and an external supply through parasitic impedance to supply/return paths dominates the process, and the resultant return bounce appears as the substrate noise.