Accurate food recognition and calorie estimation are critical for managing diet-related health issues such as obesity and diabetes. Traditional food logging methods rely on manual input, leading to inaccurate nutritional records. Although recent advances in computer vision and deep learning offer automated solutions, existing models struggle with generalizability due to homogeneous datasets and limited representation of complex cuisines like Indian food. This paper introduces a dataset containing over 15,000 images of 56 popular Indian food items. Curated from diverse sources, including social media and real-world photography, the dataset aims to capture the complexity of Indian meals, where multiple food items often appear together in a single image. This ensures greater lighting, presentation, and image quality variability compared to existing data sets. We evaluated the data set with various YOLO-based models, including YOLOv5 through YOLOv12, and enhanced the backbone with omniscale feature learning from OSNet, improving detection accuracy. In addition, we integrate a Retrieval-Augmented-Generation (RAG) module with YOLO, which refines food identification by associating fine-grained food categories with nutritional information, ingredients, and recipes. Our approach demonstrates improved performance in recognizing complex meals. It addresses key challenges in food recognition, offering a scalable solution for accurate calorie estimation, especially for culturally diverse cuisines like Indian food.

Recent years have witnessed tremendous growth in the publication of research articles as well as in the rise of new research topics. Articles get published in a streaming manner and therefore retrieving and recommending trending topics continuously by updating the trend of topics with time will be beneficial for young researchers. The proposed topic recommendation system is a clustering-based approach that utilizes an autoencoder framework for the generation of clusters. The autoencoder framework considers articles as input in a multiview framework and produces latent data in lower-dimensional space using graph attention-based encoder and decoder networks. The latent data is then partitioned with respect to its different views and finally, a single consensus overlapping partitioning is produced by satisfying all the views. Since the publication of articles is a continuous process, to update the trending topics continuously, the clustering-based approach is kept on and applied iteratively in a sliding window manner. The generated clusters are analyzed to extract the trending topics and recommendations for future scope. An article can belong to multiple topics and the proposed method is developed by considering such criteria and therefore tested with the modified version of the multilabel scientific article data ArXiv, named CSML.ArXiv. The superiority of the proposed method can be observed from its comparisons with existing methods, and a few baseline methods with respect to cluster formation, topic extraction, and trending topic evaluation.

During any natural disaster or unfortunate accident, both civilians and responders need information on an urgent basis. In such events, microblogging sites particularly Twitter plays an important role in providing real-time information. The raw form of microblog tweets is prodigiously informative but massive in size. The end-users and data analysts have to go through millions of tweets before extraction of any information. To ease the process and extract only relevant information, artificial intelligence (AI)-based techniques can be incorporated to generate summaries from the incoming information. Moreover, tweets keep on arriving continuously in a streaming manner, and therefore in ideal cases, the summaries also need to be updated continuously. In this work, we have proposed a clustering-based summary generation approach that takes multiviewed representations of data and utilizes a new variant of generative adversarial network (GAN) named triple-GAN to perform clustering. Triple-GAN consists of three networks, a generator, a discriminator, and a separator. Maintaining equilibrium among these networks requires proper parameter tuning which makes training of GAN difficult. In the literature, GAN-based techniques have been extensively applied to image datasets. In the proposed method, we have explored the usage of GAN for text data in an unsupervised manner and the analysis of the training of GAN has also been reported. The developed method opens up a new direction in utilizing GAN for solving clustering problem of text data. The proposed method is applied to two versions of four disaster-based microblog datasets and obtained results are compared with many existing and a few baseline methods. The comparative study illustrates the superiority and efficacy of the developed method.

With the emergence of the Internet of Things (IoT), there come opportunities to connect people, data, and objects, bringing dynamic changes in our way of living. At the same time, the presence of sensors and other devices around us has created a leaky ecology that is webbed. It has turned into a risk for the users and causes worry about how widely it could be adopted. Numerous projects have been put up in a similar vein, creating innovations to improve security. But, conventional cryptographic solutions are difficult to embed as these IoT devices have limited resources. Physical unclonable functions (PUFs), particularly in resource-restraining devices, have shown to be valuable for developing authentication protocols. In this work, we propose a PUF-based authentication mechanism for IoT devices. This authentication protocol also performs the key exchange between the two nodes, with the server in between. The security features of the proposed mechanism are verified using AVISPA tool.

In today’s scenario, a large number of scientific articles on various domains are being published everyday, resulting in a rapid change in the trends of research topics. Retrieving the trending topics, evaluating the trends and extracting the scope of topics could be beneficial to young researchers, which can be recommended for future scope. Publication of articles is a continuous process, and so is the evolution of topics as well as the scope. The dynamic behavior of topics can be handled by continuously updating the partitioning of incoming articles arriving in a streaming manner. This article proposes an online clustering approach utilizing the autoencoder, which is capable of handling the online stream of articles. The training is performed by considering the multiple views of articles and posing the topic modeling (TM) problem as a multiview (MV) clustering problem. In addition, we employ an evolutionary-based approach to the latent representation of data to automatically determine the number of clusters. To learn the nonlinear mapping appropriately and to generate clusters effectively, the model simultaneously optimizes the reconstruction loss and clustering loss in an MV framework. The developed method has experimented on ArXiv dataset to determine the trending topics, scope, and recommendation of topics. The superiority of the proposed method in generating clusters as well as in determining scope is shown by comparing the results with many existing and baseline methods.

To train a classifier on a specific domain, often called the target domain, we need labeled data. However, there might be non availability of the labeled data in this domain. In this scenario, we look for a related domain called the source domain, where availability of labeled data is abundant in number. The lack of availability of labeled data in the target domain poses a serious problem and several domain adaptation (DA) approaches have been put forward to cope up with this problem. Existing DA methods seek a subspace common between both the domains (source and target domains) where the distribution difference is minimal and perform manual parameter sensitivity tests to find apposite value of each parameter for their respective objective function. However, for distorted original data, obtaining a common subspace is a challenging task and condensing manual parameter sensitivity testing is also costly and a time-intensive process. To overcome these challenges, some DA methods consider particle swarm optimization (PSO) technique. However, none of the existing DA methods simultaneously tackle these challenges. Therefore, in this paper, we put forward a method called Feature and Parameter Selection approach for visual Domain Adaptation (FPSDA) to address these challenges. In FPSDA, a suitable subset of features across both the domains and an apposite value of each parameter are simultaneously chosen using a PSO approach. Moreover, to guide the PSO, the objective functions of Joint Geometrical and Statistical Alignment (JGSA) [1] method along with preserving original similarity of data is considered as an objective function for our proposed approach. Full Scale experiments on benchmark datasets for cross-domain adaptation verify that FPSDA performs better than many state-of-the-art classic machine learning and domain adaptation approaches.

Semantic hashing is a crucial component of content based search and retrieval systems. To achieve an effective semantic hashing for images, it is essential to map them to hash space in a way that preserves the semantic information. Most state-of-the-art deep semantic hashing approaches do not fully take into account the structural information and the inherent hierarchy in the dataset. Also, the distribution of hash codes is primarily driven by semantic information that comes from the supervision labels. We propose a semantic hashing framework which utilizes the hyperbolic metric learning to learn the structural and hierarchical information. This information is leveraged in the form of proxy labels for training the hashing network with the proposed novel Structure-Semantic Disagreement (SSD) loss. SSD enforces the model to learn to hash with semantic as well as structural information, leading to more robust and uniformly distributed hash codes. Tests on multiple public domain datasets establish the effectiveness of the proposed approach. Moreover, the developed SSD loss can also be applied to other classification models to improve the representation by enforcing the model to use the structure information more effectively.

In this letter, for the first time, we propose a unified framework based on attentive cycle-generative adversarial network for the synthesis of electrocardiogram (ECG) signals from the seismocardiogram (SCG) signals. The proposed attentive cycle generative adversarial network exploits dual generators and dual discriminators to learn the pattern for the synthesis of ECG from SCG and vice versa. The proposed framework is evaluated on publicly available combined measurement of ECG, breathing and seismocardiogram (CEBS) database. Subjective visual analysis and objective performance metrics demonstrate that the proposed framework can accurately derive the ECG signal from SCG signal. Since, the SCG can be recorded using a wearable and non-adhesive modality, it can provide comfort to the patients by avoiding adhesive ECG electrodes. Further, the derived ECG can help in better cardiac rhythm and arrhythmia analysis.

We propose WLAMr-DDH which is an efficient convolutional neural network based approach for deep semantic hashing for face image retrieval. The proposed model is a substantial improvement upon the end-to-end deep hash learning in the classification framework, where the model learns to generate hash codes and hash functions in a single stage. It combines the strong representation capabilities obtained from the proposed weighted lateral connections for multi-scale feature representation with our novel augmentation mask layer. The augmentation mask is a simple yet effective way to obtain weighted saliency maps at the final convolution layer which makes the prominent features to have more contribution in the final output. Also, with weight normalization via re-parametrization, which decouples the direction from magnitude, faster convergence is achieved. Results obtained from the proposed framework on publicly available datasets shows substantial improvements and outperforms several state-of-the-art methods by good margin. The approach is generic and WLAM block can be easily plugged in a multitude of image retrieval and hashing applications.

In current scenario, transfer learning or domain adaptation has been emerged as fruitful approach to handle problems of distribution mismatch between the training and test data. Standard machine learning techniques utilize labeled data for getting better performance. In practical scenario, due to scarcity of labeled data, the classifier trained on the source domain cannot be utilized efficiently for classifying the target domain data. So, there is a need to use the previously acquired knowledge from a related source domain to classify the information in the target domain. Previous works on single/multiple source domain adaptation have achieved substantial growth in tackling this concern. In this work, we have proposed a novel unsupervised multi-source based approach MSVDA for visual domain adaptation in which data from multiple labeled source domains are utilized to classify the information in the target domain containing unlabeled data. Our proposed approach MSVDA extends the existing Maximum Mean Discrepancy criteria across various source domains and also preserves the discriminative information of various source domains. Further, it learns an optimal classification that diminishes the empirical risk and enhances the consistency rate between the prediction function and the manifold. Various experiments on the two publicly available datasets with multiple-domain scenario settings (double-domain, triple-domain and quadruple-domain scenarios) have demonstrated the efficacy of our proposed method MSVDA over other existing methods.

The feature selection method is the process of selecting only relevant features by removing irrelevant or redundant features amongst the large number of features that are used to represent data. Nowadays, many application domains especially social media networks, generate new features continuously at different time stamps. In such a scenario, when the features are arriving in an online fashion, to cope up with the continuous arrival of features, the selection task must also have to be a continuous process. Therefore, the streaming feature selection based approach has to be incorporated, i.e., every time a new feature or a group of features arrives, the feature selection process has to be invoked. Again, in recent years, there are many application domains that generate data where samples may belong to more than one classes called multi-label dataset. The multiple labels that the instances are being associated with, may have some dependencies amongst themselves. Finding the co-relation amongst the class labels helps to select the discriminative features across multiple labels. In this article, we develop streaming feature selection methods for multi-label data where the multiple labels are reduced to a lower-dimensional space. The similar labels are grouped together before performing the selection method to improve the selection quality and to make the model time efficient. The multi-objective version of the cuckoo search-based approach is used to select the optimal feature set. The proposed method develops two versions of the streaming feature selection method: ) when the features arrive individually and ) when the features arrive in the form of a batch. Various multi-label datasets from various domains such as text, biology, and audio have been used to test the developed streaming feature selection methods. The proposed methods are compared with many previous feature selection methods and from the comparison, the superiority of using multiple objectives and label co-relation in the feature selection process can be established.

Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning–based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic , and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants—the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.

The dense depth estimation of a 3D scene has numerous applications, mainly in robotics and surveillance. LiDAR and radar sensors are the hardware solution for real-time depth estimation, but these sensors produce sparse depth maps and are sometimes unreliable. In recent years research aimed at tackling depth estimation using single 2D image has received a lot of attention. The deep learning based self-supervised depth estimation methods from the rectified stereo and monocular video frames have shown promising results. We propose a self-attention based depth and ego-motion network for unrectified images. We also introduce non-differentiable distortion of the camera into the training pipeline. Our approach performs competitively when compared to other established approaches that used rectified images for depth estimation.

Domain adapted machine learning is driven by the possibilities of learning from source data distribution to understand different target data distributions. An assumption is made that one application (source) domain always has enough labeled information, but the other related application (target) may contain information that is partially labeled or completely unlabeled. Therefore, it is necessary to train the target domain classifier using enough labeled information of the source domain. However, contrary to primitive assumptions, the source domain and target domain data need not have the same distribution. Therefore, we can't directly use data of source domain to train classifier for data of target domain. Existing approaches can be deprived of one or more objectives: perform geometric diffusion on the manifold, align the cross-domain distributions, preserve the discriminative information using metric learning. Here, we have proposed a novel framework that aims to meet all such objectives. In this framework, we proposed two methods, statistical and geometrical alignment using metric learning with pseudo labels (SGA-MDAP) and without pseudo labels (SGA-MDA) in visual domain adaptation. It has been demonstrated through various experiments that our framework outperforms various state-of-the-art methods over four different real-world cross-domain visual identification datasets such as PIE face, ORL face, Yale face, and Office Caltech.

The current paper addresses the online feature selection problem in multi-label classification framework where multi-labelled data with features arriving in an online fashion is considered as input. The proposed approach works in two phases, in the first phase, the best subset of features is selected from the initial available set of features using a multi-objective optimization (MOO) based feature selection technique. In the second phase of the proposed feature selection technique, a newly arrived feature is accepted or rejected based on redundancy with respect to the already selected set of features and relevancy of the arrived feature with respect to the class labels. In order to show the efficacy of the proposed algorithm, it is tested on 7 various types of multi-label datasets of different domains such as text, biology, and audio. The obtained results outperform the results obtained by state-of-the-art approaches in majority of the cases.

Data such as videos, genetic information, etc. from real-world applications reside in a high dimensional space. Before performing classification, it is required to project the data from the high dimensional space to a lower dimensional space without losing too much information. Linear discriminant analysis (LDA) is one of the most widely used methods for dimensionality reduction, that maximizes the ratio of the between-class scatter and total data scatter in the projected space using the labeled information. However, in the real world scenario, labeled information is hardly ever available in large quantities, but an abundant amount of unlabeled data is available. In this paper, we propose a Semi-Supervised Discriminant Analysis method called SSDARD, which considers the unlabeled information in the form of a k-NN graph. Different from the existing semi-supervised dimensionality reduction algorithms, our algorithm is more consistent in propagating the label information from labeled data to unlabeled data due to the use of relative distance function instead of normal Euclidean distance function to generate the k-NN graph. To find an appropriate relative distance function, we use pairwise constraints generated from labeled data and satisfy them using Bregman projection. Since the projection is not orthogonal, we require an appropriate subset of constraints. In order to select such subset of constraints, we have further developed a framework called MO-SSDARD, which uses an evolutionary algorithm while optimizing various cluster validity indices simultaneously. The experimental results on various datasets show that our proposed method is superior than various methods concerning various validity indices.

Resistive memory, also known as memristor, is an emerging potential successor to traditional CMOS charge based memories. Memristors have also recently been proposed as a promising candidate for several additional applications such as logic design, sensing, non-volatile storage, neuromorphic computing, Physically Unclonable Functions (PUFs), Content-addressable memory (CAM) and reconfigurable computing. In this paper, we explore three unique applications of memristor technology based implementations, specifically from the perspective of sensing, logic, in-memory computing and their solutions. We review solar cell health monitoring and diagnosis, describe the proposed solutions, and provide directions in memristive gas sensing and in-memory computing. For the gas sensor application, in order to determine the number of memristors to ensure a certain level of accuracy in sensitivity, a technique to optimize the sensor array based on an acceptable sensitivity variation and minimum sensitivity margin is presented. These “out-of-the-box” emerging ideas for applications of memristive devices in enhancing robustness and, at the same time, how the requirements of robust design are enabling unconventional use of the devices. To this end, the papers considers some examples of this mutual interaction.

An isolated DC-DC converter with high gain is proposed for applications using low voltage renewable energy sources. Circuit consists of an impedance network at its first stage, then a push - pull converter and a voltage doubler rectifier circuit in the final stage. This topology combines inductive coupling in impedance source network and transformer turns ratio for high gain in addition to voltage doubler. The highlights of the proposed converter topology are high gain, reduced ripple in source current and galvanic isolation between source and load which is an important requirement in solar PV system. DC voltage gain derived for the converter proves its high gain ability. Simulation results found on MATLAB/Simulink are in compliance with the waveform obtained theoretically.

The spread of surveillance cameras has necessitated the monitoring of large quantities of surveillance video feeds. A manual monitoring system is near impossible due to the large man‐hour requirements. Recently, automatic abnormal activity detection has been an area of interest among researchers. A spatio‐temporal feature, histogram of optical flow orientation and magnitude (HOFM), has produced impressive ability in detecting abnormal activities. The authors propose a novel non‐uniform spatio‐temporal region resembling parallelepipeds, from which they extract the HOFM features. Autoencoders can be configured to detect abnormal patterns. The authors have used these abilities of the autoencoders to detect abnormalities in the HOFM features extracted from their novel spatio‐temporal regions of the video feeds. The autoencoders are trained on the HOFM features of the videos containing no abnormalities. The autoencoders are then fed with the HOFM features of the videos to be tested for abnormal activities, and these are detected based on the abilities of the autoencoders to reconstruct these features. The proposed method is tested on the standard abnormality detection datasets: UCSD Ped1, UCSD Ped2, Subway Entrance, Subway Exit, and UMN.

Deep neural networks have revolutionized a variety of applications in varying domains like autonomous vehicles, weather forecasting, cancer detection, surveillance, traffic management, and so on. The convolutional neural network (CNN) is the state-of-the-art technique for many machine learning tasks in the image and video processing domains. Deployment of CNNs on embedded systems with lower processing power and smaller power budget is a challenging task. Recent studies have shown the effectiveness of field-programmable gate array (FPGA) as a hardware accelerator for the CNNs that can deliver high performance at low power budgets. Majority of computations in CNNs involve 2-D convolution. Winograd minimal filtering-based algorithm is the most efficient technique for calculating convolution for smaller filter sizes. CNNs also consist of fully connected layers that are computed using general element-wise matrix multiplication (GEMM). In this article, we propose a unified architecture named UniWiG, where both Winograd-based convolution and GEMM can be accelerated using the same set of processing elements. This approach leads to efficient utilization of FPGA hardware resources while computing all layers in the CNN. The proposed architecture shows performance improvement in the range of $1.4\times $ to $4.02\times $ with only 13% additional FPGA resources with respect to the baseline GEMM-based architecture. We have mapped popular CNN models like AlexNet and VGG-16 onto the proposed accelerator and the measured performance compares favorably with other state-of-the-art implementations. We have also analyzed the vulnerability of the accelerator to the side-channel attacks. Preliminary investigations show that the UniWiG architecture is more robust to memory side-channel attacks than direct convolution-based techniques.

Gas sensing is one of the proposed application field of memristive devices. We used a crossbar array of memristors as gas sensor using the HP labs fabricated TiO2based memristor model in an attempt to improve sensing accuracy. We introduced the possibility of reliable multiple gases detection using multiple rows of memristors as separate sensor in a crossbar array. Our experimental results show that an array of memristors can minimise measurement errors as well as provide a good redundancy measure during gas sensing. Measurements taken from the sensors are also not affected by alternate current paths problem often experienced in crossbar architecture.

We present a computationally efficient technique to build concise and accurate computational models for large (60 or more inputs, 1 output) Boolean functions, only a very small fraction of whose truth table is known during model building. We use Genetic Programming with Boolean logic operators, and enhance the accuracy of the technique using Reduced Ordered Binary Decision Diagram based representations of Boolean functions, whereby we exploit their canonical forms. We demonstrate the effectiveness of the proposed technique by successfully modeling several common Boolean functions, and ultimately by accurately modeling a 63-input Physically Unclonable Function circuit design on Xilinx Field Programmable Gate Array. We achieve better accuracy (at lesser computational overhead) in predicting truth table entries not seen during model building, than a previously proposed machine learning based modeling technique for similar Physically Unclonable Function circuits using Support Vector Machines. The success of this modeling technique has important implications in determining the acceptability of Physically Unclonable Functions as useful hardware security primitives, in applications such as anti-counterfeiting of integrated circuits.

No abstract available.

State-of-the-art commercial placement tools have as goals to optimize area, timing, and power. Over the years, several reliability oriented placement strategies have been proposed with distinct goals, such as to improve the error rate. However, we found that there are still improvements that can be made for this type of approach, to improve not only the error rates but also the performance of the placer itself. Thus, this paper proposes several improvements toward an efficient multiple faults-aware placement strategy. First, an analytical method to profile pair of gates is proposed. Second, we add another level of optimization to reduce the amount of wirelength observed after the placement is completed without jeopardizing the main objective (reliability). Third, we propose a way to manipulate white spaces between gates smartly, to separate the gates that are profiled as the most likely to reduce the error rate when paired adjacently in the circuit. Results show that a wirelength reduction of up to 61% is achieved. Also, additional reduction of the error rate of up to 23% can be achieved with only an overhead on placement execution time.

Resistive memories have simpler structures and are capable of producing highly dense memory through crossbar architecture without the use of access devices. Reliability however remains a problem of resistive memories especially in its basic read operation. This paper presents a comprehensive model for resistive devices in crossbar array as well as models for four crossbar read schemes. These models are non-restrictive and are suitable for accurate analytical analysis of crossbar arrays and the evaluation of their performance during read operation.

Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this article, we propose a novel hybrid memristor-CMOS PUF circuit and demonstrate its suitability through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially less hardware overhead than previously proposed memristor-based PUF circuits while being inherently resistant to machine learning-based modeling attacks because of challenge-dependent delays of the memristor stages. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security.

On-chip security is an emerging challenge in the design of embedded systems with intellectual property (IP) cores. Traditionally this challenge is addressed using ad hoc design techniques with separate design objectives of secure design for testability (DfT), and IP core protection. However, in this paper, we will argue that such design approaches can incur high costs. Underpinning this argument, we propose a novel design methodology, called Secure TEst and IP core Protection (STEP), which aims to address the joint objective of IP core protection and secure testing. To ensure that this objective is achieved at a low cost, the STEP design methodology employs common key integrated hardware. This hardware is incorporated in the system through an automated design conversion technique, which can be easily merged into the electronic design automation (EDA) tool chain. We evaluate the effectiveness of our proposed design methodology considering various implementations of advanced encryption standard (AES) systems as case studies. We show that our proposed design methodology benefits from design automation with high security, and protection at the cost of low area, and power consumption overheads, when compared with traditional design methodologies.

This paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF(2m). For an m input circuit, the proposed scheme can correct m ≤ Dw≤ 3m/2-1 multiple error combinations out of all the possible 2m- 1 errors, which is superior to many existing approaches. From the mathematical and practical evaluations, the best case error correction is m/2 bit errors. Tests on 80-bit parallel and, for the first time, on 163-bit Federal Information Processing Standard/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, suggest that it requires only 106% and 170% area overheads, respectively, which is lower than the existing approaches, while error injection-based behavioral analysis demonstrates its wider error correction capability.

Carbon nanotube field-effect transistor (CNTFET) is envisioned as a promising device to overcome the limitations of traditional CMOS based MOSFETs due to its favourable physical properties. This paper presents a novel six-transistor (6T) static random access memory (SRAM) bitcell design using CNTFETs. Extensive validations and comparative analyses are carried out with the proposed SRAM design using SPICE based simulations. We show that the proposed CNTFET based SRAM has a significantly better static noise margin (SNM) and write ability margin (WAM) compared to a CNTFET-based standard 6T bitcell, equivalent to isolated read-port 8T cell based on CNTFET, while consuming less dynamic power. We further demonstrate that it exhibits higher robustness under process, voltage and temperature (PVT) variations when compared with the traditional CMOS SRAM cell designs. Furthermore, metallic CNTs removal technique is used considering metallic tolerance to make the proposed SRAM design more reliable.

Memristor based logic and memories are increasingly becoming one of the fundamental building blocks for future system design. Hence, it is important to explore various methodologies for implementing these blocks. In this paper, we present a novel Complementary Resistive Switching (CRS) based stateful logic operations using material implication. The proposed solution benefits from exponential reduction in sneak path current in crossbar implemented logic. We validated the effectiveness of our solution through SPICE simulations on a number of logic circuits. It has been shown that only 4 steps are required for implementing N input NAND gate whereas memristor based stateful logic needs N+1 steps.

Power switches are increasingly becoming dominant leakage power reduction technique for sub-100nm CMOS technologies. Hence, fast and effective DFT solution for test and diagnosis of power switches is much needed to facilitate faster identification of potential faults and their locations. In this paper, we present a novel, coarse-grain DFT solution enabling divide and conquer based test and diagnosis solution of power switches. The proposed solution benefits from exponential time savings compared to previously reported solutions. Our DFT solution requires only (2⌈log2m⌈ + 3) clock cycles in the worst case for test and diagnosis for m-segment power switches. These time savings are further substantiated by effective discharge circuit design, which eliminates the possibility of false test and hence significantly reducing the charge and discharge times. We validated the effectiveness of our proposed solution through SPICE simulations on a number of ISCAS benchmark circuits, synthesized using 90nm gate libraries.

Commercial off-the-shelf (COTS) components are increasingly being employed in embedded systems due to their high performance at low cost. With emerging reliability requirements, design of these components using traditional hardware redundancy incur large overheads, time-demanding re-design and validation. To reduce the design time with shorter time-to-market requirements, software-only reliable design techniques can provide with an effective and low-cost alternative. This paper presents a novel, architecture-independent software modification tool, SMART (Software Modification Aided transient eRror Tolerance) for effective error detection and tolerance. To detect transient errors in processor data path, control flow and memory at reasonable system overheads, the tool incorporates selective and non-intrusive data duplication and dynamic signature comparison. Also, to mitigate the impact of the detected errors, it facilitates further software modification implementing software-based check-pointing. Due to automatic software based source-to-source modification tailored to a given reliability requirement, the tool requires no re-design effort, hardware- or compiler-level intervention. We evaluate the effectiveness of the tool using a Xentium processor based system as a case study of COTS based systems. Using various benchmark applications with single-event upset (SEUs) based error model, we show that up to 91% of the errors can be detected or masked with reasonable performance, energy and memory footprint overheads.

Intellectual property (IP) core based embedded systems design is a pervasive practice in the semiconductor industry due to shorter time-to-market and tougher cost competitions. Protecting the design information in these IP cores and securing test from various attacks are two emerging challenges in today's embedded systems design. Recently reported techniques address these challenges considering secure test and IP core protection separately. However, for ensuring high security during IP core functionality and also during test, joint consideration of secure test and IP core protection is much needed. In this paper, we propose a novel and unified design methodology, called STEP (Secure TEst and IP core Protection), which addresses the joint objective of secure test and IP core protection. The aim of STEP design methodology is to achieve high security at low system cost using the same key integrated hardware during test and IP core functionality. We evaluate the effectiveness of STEP design methodology considering advanced encryption standard (AES) system as a case study. We show that proposed design methodology benefits from high security and test accuracy, requiring up to 9% higher area and 20% power overheads.

The Illinois Scan Architecture (ILS) consists of several scan path segments and is useful in reducing test application time and test data volume for high density chips. In this paper, we propose a scheme of layout-aware as well as coverage-driven ILS design. The partitioning of the flip-flops into ILS segments is determined by their geometric locations, whereas the set of the flip-flops to be placed in parallel is determined by the minimum incompatibility relations among the corresponding bits of a test set, to enhance fault coverage in broadcast mode. As a result, the number of serial test patterns also reduces.

Employing thousands of cores in a single chip is the natural trend to handle the ever increasing performance requirements of complex applications such as those used in graphics and multimedia processing. System-on-chips (SoCs) platforms based on network-on-chips (NoCs) could be a viable option for the deployment of large multicore designs with thousands of cores. This paper proposes the generalized binary de Bruijn (GBDB) graph as a reliable and efficient network topology for a large NoC. We propose a reliable routing algorithm to detour a faulty channel between two adjacent switches. In addition, using integer linear programming, we propose an optimal tile-based implementation for a GBDB-based NoC in which the number of channels is less than that of Torus which has the same number of links. Our experimental results show that the latency and energy consumption of the generalized de Bruijn graph are much less than those of Mesh and Torus. The low energy consumption of a de Bruijn graph-based NoC makes it suitable for portable devices which have to operate on limited batteries. Also, the gate level implementation of the proposed reliable routing shows small area, power, and timing overheads due to the proposed reliable routing algorithm.

Concurrent error detection and correction is an effective way to mitigate fault attacks in cryptographic hardware. Recent work on differential power analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energy consumed by a working digital circuit, it is possible to gain valuable information about the encryption algorithms used and even the specific encryption keys. Thwarting such attacks requires a new approach to logic and physical designs. This paper presents a systematic approach to fault tolerant cryptographic hardware designs. Firstly, the effectiveness of the Hamming code based error correction schemes as a fault tolerance method in stream ciphers is investigated. Coding is applied to Linear Feedback Shift Registers (LFSR) based stream cipher implementations. The method was implemented on industrial standard stream ciphers, e.g. A5/1(GSM), E0 (Bluetooth), RC4 (WEP), and W7. The performance variation of stream cipher algorithms with error detection and correction was studied by synthesising the designs on Field Programmable Logic Arrays (FPGA) and Application Specific Integrated Circuits (ASIC). Further, we analyse hardware building blocks to minimise switching activity of a circuit over all possible inputs and input transitions by adding redundant gates and increasing the overall number of signal transitions. We also discuss the overhead and compositional properties of uniformly-switching circuits.

It has been recently shown that observability of design for testability techniques compromises cryptographic hardware implementation security in a straightforward manner. During test, the chip can be configured so that it is possible to observe temporal data resulting from the encryption process of a plaintext that eventually exposes the secret key. To this end, we propose a C-testable S-box implementation which is one of the most complex blocks in advanced encryption standard hardware implementation. We divide the S-box structure into a positive polarity Reed–Muller form and tested independently using a BIST circuit. The proposed structure does not use any scan chain for testability, hence avoiding the vulnerability of the chip during testing. Only 14 constant vectors are sufficient to achieve 100% fault coverage in the S-box. The C-testable feature comes with an extra hardware overhead of 15 per cent. By introducing an on-chip testing feature one can avoid potential paths for introducing unwanted access into the on-chip security blocks.

This paper presents a test generation technique for detecting stuck-at(SAF)and transition delay fault(TDF)at gate level in the finite-field systolic multiplier over GF(2m) based on polynomial basis. The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of Automatic test Pattern Generation (ATPG) tool. The complete systolic architecture is C-testable for SAF andTDFwith only six constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF and TDF coverage.

Montgomery Algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2m) for efficient implementation of Montgomery Multiplication (MM) Algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2N - 1), where N = ¿m/L¿, m is the word size andLis the digit size. No digit serial systolic architecture based on MM algorithm over GF(2m) is reported before. The architecture is also compared to two well known digit serial systolic architectures.

This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-VDDand low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An 8Kbit SRAM module with the proposed and standard 6T bitcells is simulated, including full blown parasitics using BPTM, 65 nm CMOS technology node to evaluate and compare different performance parameters. The active power dissipation in the proposed 6T design is 28% and 25% less, compared to standard 6T and 8T SRAM modules respectively.

We propose a C-testable S-box implementation which is one of the most complex blocks in AES hardware implementation. Only 12 constant vectors are sufficient to achieve 100% fault coverage in the S-box. C-testability is achieved with an extra hardware overhead of 8.2 percent.

In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring, we propose an optimum tile-based implementation for a GBDB- based Network-on-Chip (NoC). Our experimental results show that the latency and energy consumption of generalized de Bruijn graph are much less with compared to Mesh and Torus, the two common NoC architectures in the literature.

Error correction is an effective way to mitigate fault attacks in cryptographic hardware. It is also an effective solution to soft errors in deep sub-micron technologies. To this end, we present a systematic method for designing single error correcting (SEC) and double error detecting (DED) finite field (Galoisfield) multipliers over GF(2m). The detection and correction are done on-line. We use multiple Parity Predictions (PPs) to correct single errors based on the Hamming principles. Specifically, a structural approach is first presented. The predicted parities are derived from the input operands. Further, a hybrid approach is presented where the multipliers and PP circuits are synthesized, and the decoding and correction circuits are structurally combined to form the complete error correcting designs. Our technique, when compared with existing techniques, gives better performance. We show that our SEC multipliers over GF(2m) require about 100% extra hardware, whereas with the traditional SEC techniques, such as the triple-modular redundancy (TMR), this figure is more than 200%.

In this paper, we present a systematic method for the designing fault tolerant reversible arithmetic circuits for finite field or Galois fields of the form GF(2m). To tackle the problem of errors in computation, we propose error detection and correction using multiple parity prediction technique based on low density parity check (LDPC) code. For error detection and correction, we need additional garbage outputs. Our technique, when compared with traditional fault tolerant approach gives better implementation cost.

Motivated by the problems associated with soft errors in digital circuits and fault related attacks in cryptographic hardware, we presented a systematic method for designing single error correcting multiplier circuits for finite fields or Galois fields over GF(2m) in [7]. We used multiple parity predictions to correct single errors based on the Hamming principles. The problem with Hamming based error correction is the delay overhead. To mitigate the delay overhead, in this paper we present single error correction using Low Density Parity Check Codes (LDPC). The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. Our technique, when compared with existing techniques, gives better performance. We show that our Single Error Correction (SEC) multipliers over GF(2m) require slightly over 100 percent extra hardware, whereas with the traditional SEC techniques this figure is more than 200 percent.

In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as well as power efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed Monte Carlo simulations. It is observed that the 16% variation in threshold voltage results in negligible effects on static noise margin (SNM) during read operation. Experiments under different loading conditions indicate that there is reduction 2X (approximately) in power dissipation and 2X (approximately) in leakage.

Over-sampling sigma-delta analogue-to-digital converters (ADCs) are one of the key building blocks of state of the art wireless transceivers. In the sigma-delta modulator design the scaling coefficients determine the overall signal-to-noise ratio. Therefore, selecting the optimum value of the coefficient is very important. To this end, this paper addresses the design of a fourth-order multi-bit sigma-delta modulator for wireless local area networks (WLAN) receiver with feed-forward path and the optimum coefficients are selected using genetic algorithm (GA)-based search method. In particular, the proposed converter makes use of low-distortion swing suppression SDM architecture which is highly suitable for low oversampling ratios to attain high linearity over a wide bandwidth. The focus of this paper is the identification of the best coefficients suitable for the proposed topology as well as the optimization of a set of system parameters in order to achieve the desired signal-to-noise ratio. GA-based search engine is a stochastic search method which can find the optimum solution within the given constraints.

Modeling of non-linearity and uncertainty associated with rainfall-runoff process has received a lot of attention in the past years. Recently artificial intelligence techniques are used for hydrological time series modelling. Earlier studies showed this approach is effective, still there are concerns about how these techniques perform efficiently to predict the run-off with high standard of accuracy. To this end, this paper explores the ability of two artificial intelligence techniques, namely neural network auto regressive with exogenous input (NNARX) and adaptive neuro-fuzzy inference system, to model the rainfall-runoff phenomenon effectively from antecedent rainfall and runoff information. Specifically, to illustrate applicability of these techniques, two year (1994-1995) rainfall-runoff data from Brue catchment of The United Kingdom were used. The models having various input structures were constructed and the best structure was investigated with help of the proposed technique, called gamma test. Training data length selection and best input combination were carried out prior to modeling with help of gamma test. The performance of the ANFIS model in training and testing sets were compared with that of NNARX model with help of several statistical parameters. The results of the study have shown that both ANFIS and NNARX could work efficiently in rainfall-runoff modeling and can provide high accuracy and reliability in runoff prediction.

This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial-basis (PB) bit-parallel (BP) multiplier circuits over GF(2m). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of the ATPG tool. This low- complexity testing method requires (2m + 1) test vectors for detecting single stuck-at faults in the AND part and multiple stuck-at faults in the EXOR part of the multiplier circuits. The test vectors are independent of the multiplier's structure, as proposed in (T. A. Gulliver et al., 1991), but are dependent on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100 percent single stuck-at fault coverage.

This paper presents an efficient technique for synthesis and optimization of the polynomials over GF(2m), where to is a nonzero positive integer. The technique is based on a graph-based decomposition and factorization of the polynomials, followed by efficient network factorization and optimization. A technique for efficiently computing the coefficients of the polynomials over GF(pm), where p is a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graph-based representation. The technique has been applied to minimize multipliers over the fields GF(2k), where k = 2,...,8, generated with all the 51 primitive polynomials in the 0.18-mum CMOS technology with the help of the Synopsys design compiler. It has also been applied to minimize combinational exponentiation circuits, parallel integer adders and multipliers, and other multivariate bit- as well as word-level polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amounts. We also observed that the technique is capable of producing 100% testable circuits for stuck-at faults.

We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2 m ) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys® tools using UMC 0.18 micron CMOS technology library.

We present a C-testable method for detecting stuck-at (s-a) faults in the polynomial basis (PB) bit parallel multiplier circuits over GF(2m). It requires only 7 tests for detecting faults to provide 100% fault coverage, which is independent of the multiplier size. These 7 tests can be derived directly without any requirement of ATPG tools. Synopsysreg tool is used to generate ATPG based test patterns.

In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to classical CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2and 700μW respectively when synthesized in 0.18μm CMOS library which shows its effectiveness as a low-area low-power processor.

In this paper, we propose two techniques to mitigate soft error effects on the switch modules of SRAM-based FPGAs: 1) The first technique tolerates SEU-caused open errors based on a new programming method for SRAM-bits of switch modules, and 2) The second technique mitigates SEU-cause short errors in the switch modules based on a mixed programmable and hard-wired switch module structure in the FPGAs. The effects of these two techniques on the delay, area and power consumption for 20 MCNC benchmark circuits are achieved using a minor modification in VPR and T-VPack FPGA CAD tools. The experimental results show that the first technique increase reliability of connections of switch module up to 30% while the second technique decreases the susceptibility of switch modules to SEUs about 50% compared to the traditional ones

This paper presents a SEU-mitigative placement and route of circuits in the FPGAs which is based on the popular placement and route tool. The tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation and no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. We have investigated the effect of this tool on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 22%. However, it increases critical path delay and power consumptions of the circuits.

This paper presents a C-testable technique for detecting transition faults with 100% fault coverage in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m). The proposed technique requires only 10 vectors, which is independent of multiplier size, at the cost of 6% (avg.) extra hardware and three control pins. The proposed constant test vectors which are sufficient to detect both the transition and stuck-at faults in the multiplier circuits can be derived directly without any requirement of an ATPG tool. As the GF(2m) multipliers have found critical applications in public key cryptography and need secure internal testing, a built-in self-test (BIST) circuit is proposed for generating test patterns internally. This obviates the need of having three extra pins for the control inputs and also provides public-key security in cryptography. Area and delay of the testable circuit are analyzed using 0.18mum CMOS technology library from UMC

This paper presents an efficient technique for synthesis and optimization of polynomials over GF(2m), where m is a non-zero positive integer. The technique is based on a graph-based decomposition and factorization of polynomials over GF(2m), followed by efficient network factorization and optimization. A technique for efficiently computing coefficients over GF(pm), where p is a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graph based representation. The technique has been applied to minimize multipliers over all the 51 fields in GF(2k), k = 2...8 in 0.18 micron CMOS technology with the help of the Synopsys® design compiler. It has also been applied to minimize combinational exponentiation circuits, and other multivariate bit- as well as word-level polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amount.