This paper presents a dual-source energy harvesting interface for battery-free IoT devices, utilizing a serial-stacked single-inductor triple-input triple-output (SS-SITITO) buck-boost converter topology. In each charging cycle, the converter allows simultaneous power extraction from two energy harvesting sources and the usage of recycled energy in a storage capacitor. A two-dimensional maximum power point tracking (2D-MPPT) with triple-modulation realizes 98.3% accuracy in tracking the maximum power point for each input with minimal power cost. To provide sufficient output power under limited inputs, the system features energy recycling by automatically switching between sleep and active modes, and introduces a quad-phase buck-boost operation scheme, achieving up to 26mW maximum output power. To ensure self-sustainability with low quiescent power and enhanced power conversion efficiency, the circuit incorporates an edge-triggered feedback path, a power-optimized undervoltage lockout circuit, a low-voltage-supportable bandgap reference generator, and an ultra-low-power relaxation oscillator. Experimental results show a quiescent power consumption of 805nW, a 7000x power range, and a peak efficiency of 85.5%.

Targeting the simultaneous wireless charging of multiple receiver (RX) coils, we developed a coupling coefficient (${k}$) sensorless wireless power transfer (WPT) system enabled by the proposed adaptive magnetic field distributor (AMFD) IC. By simply measuring the voltages and currents on the transmitter (TX) side free of knowing the${k}$between each pair of coils, the system can optimize the current in each TX coil to optimize the generated magnetic fields at each RX coil to maximize the system efficiency ($\eta _{\mathbf {SYS}}$). A current sensor calibration (CSC) technique was also proposed to guarantee the accurate on-chip current sensing in the AMFD IC. The AMFD IC was fabricated by a$0.18~\mu $m CMOS process with 1.8 V devices. Owing to the CSC technique, an accurate on-chip current sensing could be performed with a percentage error within ±4.5 %. A WPT system consisting of 2 TX coils driven by 2 AMFD ICs and 2 RX coils was implemented. Experimental results showed that, compared with the conventional WPT method,$\eta _{\mathbf {SYS}}$in the developed system was increased from 16 % to 65 % with a load power of 276 mW when the RX coils were perpendicular to the TX coils. When the RX coils were parallel to the TX coils, a high$\eta _{\mathbf {SYS}}$of 78 % was also obtained.

This work proposes a high-step-down switched-capacitor (SC) hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. Specifically, an architecture combining a dual-path hybrid (DPH) converter at the input, and a continuous-current-input SC (CISC) stage at the output, achieves superior performance in reducing the inductor DC current ($I_{\mathrm {L,DC}}$) compared to the existing single-inductor two-flying-capacitor ($1L$-$2C_{\mathrm {F}}$) converters. Also, the converter exploits low-voltage (LV) switches to handle a substantial portion of the current, diminishing the reliance on the inductor or high-voltage (HV) switches. Consequently, this approach enhances the efficiency and on-chip power/current density. The converter, implemented in 180-nm BCD, integrates monolithic power switches, drivers, and control circuitry. It is capable of regulating an output voltage within the range of 1.2 to 3.5 V, accommodating a 12 V/24 V-input. The peak efficiency is 93% and the on-chip current density is 0.638A/mm2. The load current delivery is up to 3 A, even using a compact inductor with a DC resistance (DCR) of 200$\text{m}\Omega $.

This paper presents the design challenges and advanced circuit techniques of integrated gate drivers for non-isolated buck converters using gallium nitride (GaN) devices to achieve fast switching and high conversion efficiency. Focusing on the essential tradeoff considerations, we first explain the detailed circuit-level issues of realizing normal and safe operations regarding integration feasibility, device safety, operation reliability, and power-stage loss alleviation when driving a GaN switch. Accordingly, we review the state-of-the-art techniques for improving various aspects of the performance, including on-chip bootstrapping enhancement, over-voltage and false-switching prevention, electromagnetic interference (EMI) noise suppression, and adaptive driving optimization. We further highlight the feature advantage of distinct techniques in specific performance/function aspects, aiming to bring GaN driver design insights and providing technical references regarding the technical superiority and limitations of improving the overall converter performance.

This paper introduces a 6.78-MHz wireless power transfer (WPT) system for implantable medical devices (IMDs). The proposed dual-output resonant current-mode (RCM) rectifier cumulates energy from loosely-coupled coils and generates two output voltages (VH = 3-V, VL = 1.8-V) regulated by adaptive power control (APC) and local-loop power control. Due to transmission power regulation (TPR), the transmitter ($T_{X}$) delivers appropriate power to the receiver ($R_{X}$) to realize global-loop power control. Thus, the power transfer efficiency (PTE) is improved, especially under light load. Furthermore, zero-voltage switching and zero-current switching techniques enhance${R} _{X}$power conversion efficiency (PCE).$T_{X}$and$R_{X}$chips were fabricated in a 0.18-$\mu \text{m}$CMOS process. The measurement results show that the proposed WPT system successfully regulates outputs at VH = 3-V and VL = 1.8-V at a 1.5-cm coupling distance. With the proposed TPR, PTE is improved by 28.2% at PTOTAL = 1.6-mW, and input power is reduced by 94.8% at PTOTAL = 1-mW. The measured peak PCE and peak PTE are 85.1% and 31.3% at a coil distance of 10-mm, respectively.

Load shift keying (LSK) has been widely used in a wireless power and data transfer (WPDT) system, owing to its low cost and power consumption. It was discovered that the demodulated data can flip when the coupling coefficient ($k$) between the transmitter (TX) and receiver (RX) coils becomes less than a critical value ($k_{\mathrm {DF}}$) in a system with four basic compensation topologies (series–series, series–parallel, parallel–series, and parallel–parallel). This problem is called coupling-dependent data flipping (CDDF). Even more seriously, the transferred data cannot be recovered when$k$equals$k_{\mathrm {DF}}$. On the basis of a comprehensive circuit analysis of CDDF, a universal method applicable to all four compensation topologies was proposed. By monitoring the current through the TX coil rather than its voltage for data demodulation, CDDF can be avoided. Furthermore, a WPDT system was implemented in which the voltage information of the load resistance ($R_{\mathrm {Load}}$) was transferred to the TX side to control the source voltage for load power ($P_{\mathrm {Load}}$) regulation. Using the conventional method, CDDF along with its corresponding$k_{\mathrm {DF}}$(0.35) was verified. On the other hand, using the proposed method, the data was successfully transferred even when$k$is less than or equal to$k_{\mathrm {DF}}$. By a correct data transfer,$P_{\mathrm {Load}}$has been successfully regulated at around 1.1 W with a high system efficiency of up to 60% under the variation in$k$from 0.09 to 0.45.

We present the first demonstration of a battery-free untethered wirelessly powered sub-gram jumping robot on an insect-scale. In order to operate the insect-sized robot autonomously, the limitation in battery use emphasizes the need for a wireless power transmission system as an onboard power solution. We designed a wireless power transmission system based on inductive coupling to power the Shape Memory Alloy (SMA), which serves as an elastic energy storage element and actuator for the jumping robot. The assembled mechanical structures, onboard power and electronics yield a 2 mm (high) × 24 mm (long) × 12 mm (wide) robot with ~a weight of 216 mg. The experiments show that our jumping robot wirelessly lift-off up to 5.75 times its body length and repeats the jump around 7 times per minute. To date, out of the several untethered sub-gram insect-scale jumping robots with onboard power, this is the first wirelessly powered robot with the highest jumping performance. The novelty in this work, which addresses the engineering challenges in insect-scale jumping robots, is an untethered wirelessly powered design that achieves dynamic jumping maneuvers, and has self-righting ability.

Digital active gate drive enables the adjustable driving level in a switching transient for power devices. In this way, it is able to manage switching performance. However, to apply active gate drive in an inverter circuit, the sinusoidal output current turns out a critical problem for the design of driving profile because of its dependency on the load current. This paper aims to validate the feasibility of the digital active gate drive circuit using optimal patterns to adapt to sinusoidal output current of an inverter circuit. Firstly, a look-up table of optimal switching pattern under a certain load current condition was built in advance. It is noted that in the previous work, the online optimization system for finding the optimal pattern has been proposed and it is able to complete the searching of optimal switching pattern in an efficient time. Next, the output current of an inverter has been regulated to a sinusoidal waveform. Based on the output current, the corresponding optimal patterns are referred from the look-up table. Compared to conventional constant driving waveform, the power loss has been successfully reduced by 7% with the full optimal look-up table applied.

Load modulation is a common method to transfer data from the receiver (RX) side to the transmitter (TX) side in a magnetic resonance coupling wireless power transfer system. However, coupling-dependent data flipping (CDDF), that the data can be flipped depending on the coupling between TX and RX coils, is found for the first time using the conventional voltage monitoring across the TX coil. An analytic formula of the critical coupling coefficient (kC) of the coils that determines CDDF is derived. To avoid CDDF, a TX input voltage monitoring method is proposed. Both the CDDF in the conventional method and the correct data transfer without CDDF in the proposed method are demonstrated in the measurement.

A 3-level buck converter in the discontinuous conduction mode (DCM) is a key circuit for integrated voltage regulators to achieve high efficiency at a light load in the stand-by mode operation of microprocessors. In this paper, fundamental circuit characteristics including the conversion ratio and transfer function are derived for the first time, enabling the design of controllers for 3-level buck converters in the DCM. The derived transfer function is verified by time-domain small-signal-injection simulation. Similar to conventional 2-level buck converters, 3-level buck converters in the DCM have a flrst-order lag transfer function, while 3-level buck converters in the continuous conduction mode (CCM) have a second-order lag transfer function, suggesting that different controllers are required for the DCM and CCM.

A 1-Mbps, 315MHz OOK transceiver in 40-nm CMOS for body area networks is developed. Both a 38-pJ/bit carrier-frequency-free intermittent sampling receiver with -55dBm sensitivity and a 36-pJ/bit transmitter applied dual supply voltage scheme with -20dBm output power achieve the lowest energy in the published transceivers for wireless sensor networks.

A low voltage buck DC-DC converter (0.45-V input, 0.4-V output) with on-chip gate boosted (OGB) and clock frequency scaled digital PWM controller is designed in 40-nm CMOS process. The highest efficiency to date is achieved at the output power less than 40μW. In order to compensate for the die-to-die delay variations of a delay line in the proposed digital PWM controller, a linear delay trimming by a logarithmic stress voltage (LSV) scheme with good controllability is also proposed and verified in measurement.

We demonstrate ultrathin, ultraflexible, large-area pressure sensors based on an organic transistor integrated circuit. A 10-μm-thick plastic film with an organic transistor active matrix is developed that can be bent to a bending radius of less than 1 mm to create an electrical artificial skin (E-skin). The thin-film, flexible pressure-sensor matrix is implemented on a curved surface, and the spatial distribution of pressure is successfully obtained in real time.

To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDDscaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDminof FFs is higher than the optimum supply voltage. In HVFF, the VDDof combinational logic gates is reduced below the VDDminof FFs while keeping the VDDof FFs at their VDDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage.

In this paper, a fully integrated low voltage charge pump for thermoelectric energy harvesters is presented. The proposed dual-mode architecture achieves both the low startup voltage in a startup mode and high conversion efficiency in a normal operation mode without off-chip inductors and capacitors. In the measurement, the proposed circuit successfully converts 120-mV input to 770-mV output with 38.8% conversion efficiency.

A design methodology for sub-0.5V crystal oscillators is shown to realize an all-sub-0.5V ultra low power RF transceiver for wireless sensor networks. To reduce the minimum operating voltage (VDDmin) of the crystal oscillator, both the optimization of the gate width of the CMOS inverter in the crystal oscillator and the reduction in gate length by CMOS technology scaling are required. In accordance with the developed design methodology, a 39MHz crystal oscillator is designed and fabricated in a 40nm CMOS. The measured power consumption is 4.1μW at 0.35V and 39MHz, and the power supply voltage is the lowest among the previously reported crystal oscillators.

New measurement system for characterizing within-die delay variations of individual standard cells is presented. The proposed measurement system are able to characterize rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65 nm 1.2V CMOS process. Seven types of standard cells are measured with 60 DUTs for each type. Good correlations of within-die delay distributions between measured and Monte Carlo simulated results are observed. The measured results of rising and falling delay are of great use to the modeling of standard cell library of deep-submicrometer process. By virtue of the proposed scheme, the relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.

New characterizing system for within-die delay variations of individual standard cells is presented. The proposed characterizing system is able to measure rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65nm CMOS process. 7 types of standard cells are measured with 60 DUT's for each type. Thanks to the proposed system, a relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.

In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process.

Many of us in the field of ultra-low-Vddprocessors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vddwith a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vthdefinitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's Vddand energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need Vddto compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold Vddcan be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-Vddsystems. The outlined pitfalls also shed light on future directions in this field.

Organic electronics is attracting a lot of attention for large-area pervasive electronics applications, because organic transistors can be fabricated using printing technologies on arbitrary substrates and this enables both high-throughput and low-cost production. In this paper, some examples of the large area electronics with the organic transistors including a wireless power transmission sheet and a communication sheet are presented. Challenges for future large area electronics are also described.

An asynchronous threshold detector for DC-960 MHz band impulse ultra-wideband (UWB) receiver is proposed in this paper. It features a DC power-free pulse discriminator. The proposed architecture in 90 nm CMOS achieves the lowest power consumption of 0.19 mW and energy consumption of 1.9 pJ/bit at 100 Mbps in the UWB receiver.

A 3D-integrated Solid State Drive (SSD) with the boost converter can achieve both the low power and the fast write-operation at the small die area of the NAND flash memory. The performance of the boost converter, however, is critically affected by the inductor, because the output voltage of the boost converter, the rising time, and the energy consumption during the boost are determined by the inductor. Therefore, this paper proposes a design methodology of the inductor of the boost converter for the 3D SSD. By using the boost converter with the optimized inductor, the energy during write-operation of the proposed 1.8-V 3D-SSD is decreased by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump.

In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of minimum operating voltage (VDDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring oscillators (RO's). The measured average VDDmin of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1Mega, which indicates the difficulty of the VDD scaling in the large scale subthreshold logic circuits. The dependence of VDDmin on the number of stages is calculated with the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, which confirm the tendency of the measurement.