Microwave spectroscopy holds great potential for the development of non-invasive biomedical sensors capable of penetrating tissues and detecting changes in biomarker permittivity. However, the surrounding tissue can interfere with the signal, reducing selectivity when targeting subcutaneous volumes. Depth spectroscopy, using sensors such as open-ended coaxial probes (OCPs), has been proposed to access different tissue layers. Despite their promise, OCPs face challenges in practical, out-of-lab applications. In this paper, we present a sensor interface with tunable sensing volume. Through dual-mode excitation, we demonstrate that the sensor can detect two distinct depths: 0.62 mm and 1.4 mm, highlighting the suitability of this technique for developing sensor interfaces for depth spectroscopy.

Designing integrated inductors can be a resource-intensive task, requiring computationally demanding electromagnetic simulations and relying on libraries constrained by the capabilities offered by foundries. In this paper, we present a surrogate-based artwork generator for integrated inductor design: Conure. The surrogate model is based on a single artificial neural network that predicts the inductor’s performance over a frequency range of 1MHz to 50GHz from geometric parameters. It is capable of processing diverse coil configurations for the entire frequency range in a single model. Additionally, the optimization algorithm NSGA-II has been applied to derive design parameters that meet desired specifications. Conure is a promising approach for complete CMOS RF passive component design. The presented model is trained using data from electromagnetic simulations of coplanar symmetric octagonal inductors in 65nm CMOS. However, Conure can be scaled to other processes, inductor geometries, and frequencies.

In this paper we explore the noise and linearity limitations of a delay line based frequency to voltage converter (FVC) for use in an analog to digital converter (ADC) linearization system. Phase noise due to the delay line is the main source of noise in the FVC. In this paper we derive the relationship between the phase noise and the output voltage noise of the FVC. Furthermore, we characterize the constraints on the design of the delay line to ensure good linearity and derive a relationship between the series resistance of the buffer driving the output filter and the total harmonic distortion (THD). Simulation results obtained using a commercially available 90 nm process design kit (PDK) show good agreement between the predicted noise and linearity and the simulated results.

In this paper, a design of the first-order Frequency-based Delta-Sigma Modulator (FDSM) utilizing multi-phase quantizer is presented. The VCO (Voltage-Controlled Oscillator) which behaves as a voltage-to-phase integrator will be proposed to generate multiple output phases. Each phase output from the VCO drives a counter using the proposed CMSA-FF (Current-Mirror Sense-Amplifier Flip-Flop), producing a total counted number of phase transitions higher than the single-phase FDSM. This will help to significantly improve the FDSM resolution. The circuits are designed using a TSMC 90nm CMOS process.

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

A digitally controlled resonant tank oscillator with loop antenna radiating inductor offers high energy efficiency in BFSK transmission, however suffers from frequency drift. Here we present a fast-settling adaptive digital architecture for dual-loop frequency locking of a BFSK transmitter. The method uses interleaved frequency-locked loops (FLL) that allow fast and energy-efficient direct digitally controlled oscillator (DCO) frequency modulation at a data rate exceeding the settling time of the frequency adaptation, while maintaining frequency regulation. The fully digital FLL architecture retains the dual-loop adapted states between transmission bursts, allowing for energy efficient low duty cycle transmissions with minimal or no settling transient at the beginning of a transmission burst. Analysis and simulation results are presented of the architecture operating in the 402-405 MHz MICS band for biomedical applications, indicating locking at 130 kHz frequency resolution at 115 μs settling for 125 kbps BFSK telemetry.

A fully differential rail-to-rail Operational Transconductance Amplifier (OTA) with improved DC-gain and reduced power consumption is proposed in this paper. By using the adaptive biasing circuit and two differential inputs, a low stand-by current can be obtained together with reduced power consumption. The DC-gain of the proposed OTA is improved by adding a partial feedback loop. A Common-Mode Feedback (CMFB) circuit is required for fully differential rail-to-rail operation. Simulations show that the OTA topology has a low stand-by power consumption of 96μW and a high FoM of 3.84 [(V/μs.pF)/μW] for a load capacitor of 10pF.

A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the pulse generator stage as well as the delay of the set-reset (SR) latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed flip-flop is implemented in a 65 nm CMOS technology.

In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65 nm standard models are used for simulations.

This paper presents two novel methods for sampling the backscatter in an impulse radar system. The authors have called the two related methods for swept threshold and stochastic resonance sampling. The samplers are simple, mostly digital circuits which are not clocked, but instead utilize continuous-time signal processing. Since fine-pitch CMOS is not very good for analog processing, but instead has very fast digital logic, the samplers are well suited for this technology. An implementation in 90 nm CMOS is described and measurements which confirm a working 23 GHz sampler are shown