We propose an efficient multicast cell-scheduling algorithm, called multiple-slot cell-scheduling algorithm, for multicast ATM switching systems with input queues. Cells in an input-queueing system are usually served based on the first-in-first-out (FIFO) discipline, which may have a serious head-of-line (HOL) blocking problem. Our algorithm differs from previous algorithms in that we consider the output contention resolution for multiple time slots instead of the current time slot only. Like a window-based scheduling algorithm, our algorithm allows cells behind an HOL cell to be transmitted prior to the HOL cell in the same input port. Thus, HOL blocking can be alleviated. We have illustrated that the delay-throughput performance of our algorithm outperforms most of those algorithms that consider only the output contention resolution for the current time slot. We also present a simple and efficient architecture for realizing our algorithm, which can dramatically reduce the time complexity. We believe that the proposed architecture is very suitable for multicast asynchronous transfer mode (ATM) switching systems with input queues.

Single-stage Beta interconnection networks have been proposed for connecting processing elements in multiprocessing systems. An efficient data routing strategy has been designed. Faulty switching elements in the network can be automatically diagnosed. Its fault-tolerant capability is achieved by allowing data to recirculate the network several more passes with the presence of faults. Two parameters are taken into account to evaluate the network, i.e., communication delay d and degree of fault tolerance k. It has been shown elsewhere that k + 1 ≤ d. We have derived, a class of single-stage Beta networks which have been shown to possess the optimal fault tolerance property, i.e., k = d -1.