Interferometric Synthetic Aperture Radar (InSAR) is a measuring technology that uses the phase information contained in the images of the Synthetic Aperture Radar (SAR). InSAR has been recognized as a potential method for digital elevation models (DEMs) generation and ground surface deformation measurement. Nonetheless, the quality of InSAR data is influenced by many critical factors. Including image co-registration, interferogram generation, phase unwrapping and geocoding. Image co-registration aims to align two or more images so that the same pixel in each image corresponds to the same point of the target scene. This study proposes a new algorithm for improving Image co-registration and interferogram generation of SAR using learning-based images super-resolution (SR). We show that our approach improves the conventional approaches.

Dynamic ensemble selection techniques, on a case by case basis, select a subset from the pool of available ensembles to classify the unknown exemplars. This selection process is usually based on a criterion that the selected ensembles should meet. In this paper, first we present a method to improve the performance of the available ensembles by regulating their sensitivity behavior towards the noise perturbations to their respective training sets. Then we present a set of dynamic ensemble selection criteria to evaluate these ensembles based on their similarity and diversity of behavior compared to other ensembles when an unknown case is presented to them. We then present the results of the experiments conducted over several classification data sets (some ill-defined problems are included as well). The results show improvements compared to the state-of-the-art dynamic selection techniques.

In this paper, the effects of regularization on the generalization capabilities of a neural network model are analyzed. We compare the performance of Levenberg-Marquardt and Bayesian Regularization algorithms with and without post-training regularization. We show that although Bayesian Regularization performs slightly better than Levenberg-Marquardt, the model trained using Levenberg-Marquardt holds more information about the data set which by proper post-processing regularization can be extracted. This post-processing regularization imposes smoothness and similarity.

Restricted Boltzmann Machine is a fundamental method in deep learning networks. Training and generalization is an ill-defined problem in that many different networks may achieve the training goal; however each will respond differently to an unknown input. Traditional approaches include stopping the training early and/or restricting the size of the network These approaches ameliorate the problem of over-fitting where the network learns the patterns presented but is unable to generalize. Bayesian regularization addresses these issues by requiring the weights of the network to attain a minimum magnitude. This ensures that non-contributing weights are reduced significantly and the resulting network represents the essence of the inter-relations of the training. Bayesian Regularization simply introduces an additional term to the objective function. This term comprises the sum of the squares of the weights. The optimization process therefore not only achieves the objective of the original cost (i.e. the minimization of an error metric) but it also ensures that this objective is achieved with minimum-magnitude weights. We have introduced Bayesian Regularization in the training of Restricted Boltzmann Machines and have applied this method in experiments of hand-written numbers classification. Our experiments showed that by adding Bayesian regularization in the training of RBMs, we were able to improve the generalization capabilities of the trained network by reducing its recognition errors by more than 1.6%.

In this work we investigate the effects of a workload's memory activity and its relation to the application's power requirements. We use the term "memory transitions" to refer the number of bits altered when a write occurs as compared to the previous value of the target memory cell(s). Memory transitions require a definite energy and this has been confirmed in this study which shows that there exists a correlation between processor power and the amount of memory transitions. Using real power readings from running benchmarks on an Intel i7-3770 processor and comparing the results to the memory transition footprint shows that for certain applications the correlation between power and memory transitions is more pronounced than the correlation between power and the number of writes.

In this paper, we improve the results based on a Neural Network-based model that predicts an enzyme (Aldose Reductase) inhibitory activity of a group of compounds. The improvement is due to the judicial selection of ensembles of trained Neural Networks to contribute to the final model. The method is validated on a family of compounds that is different from the families which were used in the training of the model. The results confirm an accurate, chemical-family-independent method that can predict Aldose Reductase inhibitory activity with excellent accuracy.

The main contributors to message delivery latency in message passing environments are the copying operations needed to transfer and bind a received message to the consuming process/thread. A significant portion of the software communication overhead is attributed to message copying. Recently, a set of factors has been leading high- performance processor architectures toward designs that feature multiple processing cores on a single chip (a.k.a. CMP). The Cell Broadband Engine (BE) shows potential to provide high-performance to parallel applications (e.g., MPI applications). The Cell's non-homogeneous architecture along with small local storage in SPEs impose restrictions and challenges for parallel applications. In this work, we first characterize various data delivery mechanisms in the Cell BE processor; then, we propose techniques to facilitate the delivery of a message in MPI environments implemented in the Cell BE processor. We envision a cluster system comprising several cell processors each supporting several computation threads.

It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partitioning technique which considers both the controller and the datapath together. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. Here, we propose a technique which uses simulated annealing to efficiently partition a FSMD for power gating. We use this non-linear model to partition 4 application circuits. We then develop a framework to estimate the potential power savings. The estimation framework shows that up to 69% static power savings and 30% dynamic power savings can be expected.

The emergence of computational grids has lead to an increased reliance on task schedulers that can guarantee the completion of tasks that are executed on unreliable systems. There are three common techniques for providing task-level fault tolerance on a grid: retrying, replicating, and checkpointing. While these techniques are varyingly successful at providing resilience to faults, each of them presents a tradeoff between performance and resource cost. As such, tasks having unique urgency requirements would ideally be placed using one of the techniques; for example, urgent tasks are likely to prefer the replication technique, which guarantees timely completion, whereas low priority tasks should not incur any extra resource cost in the name of fault tolerance. This paper introduces a placement and selection strategy which, by computing the utility of each fault tolerance technique in relation to a given task, finds the set of allocation options which optimizes the global utility. Heuristics which take into account the value offered by a user, the estimated resource cost, and the estimated response time of an option are presented. Simulation results show that the resulting allocations have improved fault tolerance, runtime, profit, and allow users to prioritize their tasks.

In this paper, we use the CoDeL platform to develop test circuits and analyze the potential and performance impact of power gating individual registers. For each register, we examine the percentage of clock cycles for which they can be powered off, and the loss of performance incurred as a result of waiting for the power to be restored. Using a time-based technique to determine when the registers can be turned off results in 15% bit cycles saved at a performance loss of 2%. We then propose a method, which uses the information available to the CoDeL compiler to predict when the components can be powered off. Results show that our CoDeL assisted gating scheme allows up to 58% more power gated bit cycles than the time-based technique, with similar performance loss

The knapsack-based task scheduler has been previously shown to provide Quality of Service to malleable tasks on computational grids. In this study, we measure the sensitivity of the knapsack-derived schedules to variations in the prescribed allocation policies and their corresponding utility functions. In particular, we explore the effects of varying the strengths of an external user-specified monetary metric, an intrinsic estimated response time mediated by nearness to completion time metric, and of varying the shape of a sigmoidal normalizing utility function. The results of our analyses show that the knapsack strategy results in schedules that are consistent with the defined allocation policies. We conclude by indicating the recommended metric weights, that is, those that produce desirable schedule characteristics.

We present a platform for rapidly developing power efficient hardware architectures. We have developed a new language, called CoDeL, which allows hardware description at the algorithm level, and thus dramatically reduces design time. We have extended CoDeL to automatically insert clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. To estimate the power savings, we have developed an estimation framework, which is shown to be consistent with the power savings obtained using statistical power analysis using Synopsys tools. To evaluate our platform we use the CoDeL implementation of a two-dimensional discrete wavelet transform using the lifting technique. A simulation based power analysis on the designed circuit shows that CoDeL's clock gating reduces the power dissipation by up to 80%

In this paper, we present a mechanism to obtain a neural network-based model that predicts an enzyme inhibitory activity of a group of compounds. The mechanism selects the compounds, among a sparse set of, that should be used to obtain models of the inhibitory activity of interest. That is, the mechanism is aimed at the selection of a training set of compounds which ensures that the training of a neural network-based model results in a system capable of generalization.

In this work an optimal algorithm is presented for bounding dependencies in coarsely quantized systems for the purposes of fault detection. Coarse quantization implies the need to analyze signals for which the standard /spl Delta//sup 2//12 approximation for quantization noise cannot be applied. This creates significant difficulties when it comes to retrofitting analytic fault detection and identification (FDI) approaches to existing large-scale engineering plants that have coarsely quantized status data, particularly in situations when no system models exist and/or it is cost-prohibitive to replace the exist status data sampling sub-systems. No methodology has been reported in the literature for optimal fault detection for the case of coarsely quantized signals. This work presents such an optimal approach. The theoretical results are operational validated by applying the algorithm to perform fault detection on one year's data obtained from a real-world large-scale engineering plant.

A new heuristic for solving the multichoice multidimensional knapsack problem (MMKP) is presented in this paper. The MMKP is first reduced to a multidimensional knapsack problem (MKP). A linear programming relaxation of the resulting MKP is solved, and a series of new values for the variables is computed. These values, pseudo-utility values, and resource value coefficients computed as well, are used in order to obtain a feasible solution for the original MMKP. Finally, the quality of the feasible solution is improved using the pseudo-utility values and the coefficient values of the objective function. Numerical results show that the performance of this approach is superior to that of previous techniques.

An algorithm is proposed for determining if a pattern classifier/recognizer can be developed based upon a sparse set of exemplars. Specifically, we address fault classifications issues associated with cable television distribution networks and use signatures of observed faults to train our neural networks. Our focus is to derive a training set of exemplars which will ensure that the training of a neural network classifier will result in a system capable of generalization.

An approach aiming to formulate the mobile network resource allocation problem is proposed here. In order to formulate the resource allocation problem, the way network resources are to be counted is defined. Then, the resource allocation problem is expressed as a multidimensional knapsack problem. The knapsack problem is relaxed and a constrained optimisation linear programming problem is obtained. A series of pseudo-utility values is obtained from the solution of the linear programming problem. The pseudo-utility values are used to establish an order by which the calls/terminals/users are to be attended by the network.

Abstract With the increasing uniprocessor and symmetric multiprocessor computational power available today, interprocessor communication has become an important factor that limits the performance of clusters of workstations/multiprocessors. Many factors including communication hardware overhead, communication software overhead, and the user environment overhead (multithreading, multiuser) affect the performance of the communication subsystems in such systems. A significant portion of the software communication overhead belongs to a number of message copying operations. Ideally, it is desirable to have a true zero‐copy protocol where the message is moved directly from the send buffer in its user space to the receive buffer in the destination without any intermediate buffering. However, due to the fact that message‐passing applications at the send side do not know the final receive buffer addresses, early arrival messages have to be buffered at a temporary area. In this paper, we show that there is a message reception communication locality in message‐passing applications. We have utilized this communication locality and devised different message predictors at the receiver sides of communications. In essence, these message predictors can be efficiently used to drain the network and cache the incoming messages even if the corresponding receive calls have not yet been posted. The performance of these predictors, in terms of hit ratio, on some parallel applications are quite promising and suggest that prediction has the potential to eliminate most of the remaining message copies. We also show that the proposed predictors do not have sensitivity to the starting message reception call, and that they perform better than (or at least equal to) our previously proposed predictors. Copyright © 2002 John Wiley & Sons, Ltd.

Consider an interconnection network and the following situation: Every node needs to send a different message to every other node. This is the total exchange or all-to-all personalized communication problem, one of a number of information dissemination problems known as collective communications. Under the assumption that a node can send and receive only one message at each step (single-port model), it is seen that the minimum time required to solve the problem is governed by the status (or total distance) of the nodes in the network. We present a time-optimal solution for any Cayley network. Rings, hypercubes, cube-connected cycles, and butterflies are some well-known Cayley networks which can take advantage of our method. The solution is based on a class of algorithms which we call node-invariant algorithms and which behave uniformly across the network.

Total exchange (or multiscattering) is one of the important collective communication problems in multiprocessor interconnection networks. It involves the dissemination of distinct messages from every node to every other node. We present a novel theory for solving the problem in any multidimensional (cartesian product) network. These networks have been adopted as cost-effective interconnection structures for distributed-memory multiprocessors. We construct a general algorithm for single-port networks and provide conditions under which it behaves optimally. It is seen that many of the popular topologies, including hypercubes, k-ary n-cubes, and general tori satisfy these conditions. The algorithm is also extended to homogeneous networks with 2/sup k/ dimensions and with multiport capabilities. Optimality conditions are also given for this model. In the course of our analysis, we also derive a formula for the average distance of nodes in multidimensional networks; it can be used to obtain almost closed-form results for many interesting networks.

Abstract — During the design of microprocessor-based systems, once the system architecture has been decided and the major components (processors, memories, IO devices) have been selected from a component library, it is necessary to design inter-face logic to integrate the system. Such an interface design can be carried out based on the protocols used by the components. This paper addresses the problem of determining the feasibility of a design prior to synthesis. A design is called feasible if it achieves the desired functionality and satisfies the given environmental constraints. Because timing is an important aspect of a correct design, protocols are described using timed signal transition graphs, an interpreted Petri net. It is shown here that the feasi-bility of designs whose corresponding behavior is periodic can be studied using a technique called timing analysis for synthesis. I.

Allocating nodes in a concurrent computer system depends on the topology of the system. In this work, we present a number of processor allocation strategies for Hypercycle based concurrent systems. Hypercycles is a class of multidimensional interconnection networks which includes such widely used networks as the binary n-cubes, k-ary n-cubes, generalized hypercubes etc. The allocation strategies presented include a statically optimal first-fit allocation, a suboptimal-first fit, and strategies with extended search space through the inclusion of additional search lists formed by permuting the base through which a hypercycle is defined. For all these strategies, we examine their optimality and present simulation results characterizing their performance relative to each other.>

In many complex problems a particular decision making procedure is often required in order for a final solution to be found. Such a procedure may consist of a large number of intermediate steps where "local" decisions must be taken and can be sometimes represented as a decision tree. When that structure is used the final solutions obtained vary depending on the available information. However, if the same model is applied many times, experimental data can be collected and observations on the acquired knowledge can be made. In this work, we present a probabilistic approach for reducing the number of decisions (tests) that are required in a particular decision making situation. Specifically, we consider that a problem is structured as a complete binary balanced decision tree, the interior nodes of which correspond to decision points; the paths of the tree represent different decision making processes. By assuming that there exists sufficient probabilistic information concerning the decisions-at the interior nodes, we propose techniques in order to minimize the average number of these decisions when we search for a final solution.>

In this work we present a brief overview of Hypercycles[4,5,8] can be considered as the Hypercycies which is a class of products of "basic " graphs that use a rich set of multidimensional graphs. These graphs can be component "basic " graphs ranging in complexity used to structure Concurrent Multiprocessor from simple rings to the fully connected ones. Systems so as to best match the requirements of Because the "basic " graphs are defined, we are a given application. able to provide analytical expressions for We present the backtrack-to-the-origin-and- routing. Our goals are retry routing as applied to Hypercycles, as well (a) To provide computer interconnection as its performance evaluation based on networks that match the node simulations. requirements of a given embedded system. Also, we present the a First Fit processor (b) To increase throughput of a given network allocation strategy for Hypercycle-based by providing routing expressions that can Multiprocessors, and prove that such a strategy be computed analytically (and hence are is statically optimal. candidates for VLSI implementation) and Finally, we discuss the implementation which provide a number of alternate paths status of a router component for the backtrack- from a source to a destination. to-the-origin-and-retry routing. The Hypercycles, being regular graphs. retain the advantages of easy routing and 1. Introduction regularity. Yet, since we are dealing with a class, Message passing concurrent computers such rather than isolated graphs, we have the

Hypercycles, a class of multidimensional graphs that are generalizations of the n-cube are presented. These graphs are obtained by allowing each dimension to incorporate more than two elements and a cyclic interconnection strategy. Hypercycles offer simple routing and the ability, given a fixed degree, to choose among a number of different size graphs. These graphs can be used in the design of interconnection networks for distributed systems tailored specifically to the topology of a particular application. A back track-to-the-origin-and-retry routing, whereby paths that block at intermediate nodes are abandoned and a new attempt is made, is presented. Intermediate nodes are chosen at random at each point from among those that form the shortest paths from a source to a destination. Simulation results that establish the performance of a variety of configurations are presented. An initial attempt at constructing a hypercycle-based router is discussed.>

The authors present results of attempts to introduce learning for a class of neural networks that has been proven to be asymptotically stable and that can be used to model several existing structures in the central nervous system (e.g., cerebellum). Specifically, the authors discuss the structure of this class of asymptotically behaving neural networks, introduce a Hebbian learning rule that can be used to modify both the inhibitory and excitatory synapses, and use this rule to train a simple network from this class in an XOR problem. The simulator and its user interface that are under development for the study of such problems are also presented

In this work, we present the overall structure of DAME, which is an expert system capable of configuring and designing customized microprocessor based systems from original specifications.

An overview is presented of a micromanipulator vision system for use in automating various functions during the testing of a wafer for semiconducting parameters and inspection of VLSI circuits. Positioning the probe and touching a test pad are the chief concern of the work desired. A brief description of the experimental setup is given. The image processing techniques used in identifying and controlling the location of various components such as the probes and the test pads are discussed. The vision modules and an expert system using hierarchical plan generation to control the sequence of plans are included.>

A collision-free variation (CSMA/CF) of the CSMA/CD (carrier-sense multiple access with collision detection) protocol was proposed by C.W. Wong (1985). This variation uses two separate channels for network acquisition; data transmission can be performed in parallel with the current transmission, the idle period is greatly reduced, and consequently the system throughput is increased. The authors describe an analytical method to calculate the throughput of this collision free protocol. The results are then compared with the throughput of the original CSMA/CD access method. It is concluded that the throughput of the collision-free protocol is greatly increased, mostly due to the application of prescheduling and parallelism.>

In this work, we present the structure of the H-Network, which is a high data rate (∼ 7 Mbytes/s) local area network used to provide point to point and broadcast communication for the Homogeneous Multiprocessor. We also present the analysis, and obtain the throughput and packet delay characteristics for the H-Network operating under CSMA/CD with adaptive and nonadaptive backoff protocols.

The structure of the homogeneous multiprocessor where each processing element owns its local memory and has access to the memory elements of its two immediate neighbors via dypamically created extended buses is discussed. The algorithm that controls the operation of the extended buses is presented and liveness and safeness properties for the algorithm are proven. Finally, potential uses of the homogeneous multiprocessor, in the fields of image processing and neural network simulation are outlined.