In this paper we present a method for determining the feasible set of analog design problems and we propose an efficient method for their verification. The verification method presented relies on the formulation of the analog circuit design problem as a convex optimization problem in both the design variables and the performance specifications. Since the design is convex not only in the design variables but also in the specification parameters, we observe that the feasible sets are convex and points at the boundary can be found by solving a single convex optimization problem. We also show that feasible sets can be very well approximated with a polyhedron and therefore defined by a finite set of points. The implication of the latter is that new verifications do not need to be run for every new instantiation of a synthesized analog cell.

We present a method for automated design of CMOS switched-capacitor filters (SCFs) from user defined top-level specifications to component sizes and physical layout. In other words, we present a complete top-down design flow for SCFs. The method is based on careful analysis and modeling of the SCF using analog circuit design and system engineering expertise, formulating design constraints in a special convex form, and numerical optimization (geometric programming).

In this paper we present a method for the design of analog-todigital converters (ADCs). This method computes the sizes of the different components (transistors, capacitors, etc.) in a predefined ADC topology so that the design specifications are met in the desired process technology.The method is based on formulating the ADC design constraints such as specifications on power, signal-to-noise ratio (SNR), area, and sampling frequency in special convex form in terms of the component sizes of the ADC and intermediate design variables. More specifically, we cast the problem of sizing the components of the ADC as a geometric program. Therefore, all design constraints are formulated as posynomial inequality or monomial equality constraints. Very efficient numerical algorithms are then used to solve the resulting geometric program and to compute the component sizes of an ADC that meets the desired specifications. The synthesis method is fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected.This paper introduces the concept of hierarchical problem formulation within a geometric programming framework. This modular formulation allows a high re-use of the ADC posynomial model.

Despite the fact that more and more electronic design is comprised of analog and mixed signal content, the design flows and methodologies in this area are lagging behind the pace of innovation in digital design. For sure, analog designers are in shorter supply, but this only makes the need for improvements and efficiency that much greater. Only of late have we seen production-worth attempts at functions such as analog synthesis and optimization reach the market. What is needed in today's analog design flow? What are the key technologies that are missing? How does the existing “food chain” need to work together to drive greater efficiencies?

We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result, the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs or globally optimal tradeoffs among competing performance measures such as power, open-loop gain, and bandwidth. Our method, therefore, yields completely automated sizing of (globally) optimal CMOS amplifiers, directly from specifications. In this paper, we apply this method to a specific widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can he used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.

We present an efficient method for optimal design and synthesis of CMOS inductors for use in RF circuits.This method uses the the physical dimensions of the inductor as the design parameters and handles a variety of specifications including fixed value of inductance, minimum self-resonant frequency, minimum quality factor, etc. Geometric constraints that can be handled include maximum and minimum values for every design parameter and a limit on total area.Our method is based on formulating the design problem as a special type of optimization problem called geometric programming, for which powerful efficient interior-point methods have recently been developed.This allows us to solve the inductor synthesis problem globally and extremely efficiently.Also, we can rapidly compute globally optimal trade-off curves between competing objectives such as quality factor and total inductor area.We have fabricated a number of inductors designed by the method, and found good agreement between the experimental data and the specifications predicted by our method.

Presents a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular, the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal trade-off curves between competing objectives such as phase noise and power.

Article Free Access Share on GPCAD: a tool for CMOS op-amp synthesis Authors: Maria del Mar Hershenson Electrical Engineering Department, Stanford University, Stanford CA Electrical Engineering Department, Stanford University, Stanford CAView Profile , Stephen P. Boyd Electrical Engineering Department, Stanford University, Stanford CA Electrical Engineering Department, Stanford University, Stanford CAView Profile , Thomas H. Lee Electrical Engineering Department, Stanford University, Stanford CA Electrical Engineering Department, Stanford University, Stanford CAView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 296–303https://doi.org/10.1145/288548.288628Online:01 November 1998Publication History 45citation513DownloadsMetricsTotal Citations45Total Downloads513Last 12 Months41Last 6 weeks5 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF