This paper proposes a switched-capacitor DC-DC converter with a self-recovery hysteresis control mechanism to deal with both steplike and spike-like load fluctuations. The converter is fabricated in a commercial 65 nm CMOS low-power (LP) process. Our converter can maintain efficiency above 69% over a load current range of 0.11~ 8.0mA with a total capacitance of 1 nF. The converter recovers quickly from a current spike of as high as 21mA within only 92 mV of voltage drop.

This paper presents measurement results of a flash ADC that utilizes offset voltages as references. To operate the minimum number of comparators, we select the target comparators based on the rankings of the offset voltage. We present performance improvement by tuning offset voltage distribution using multiple comparator groups under the same power. A test chip in a commercial 65 nm GP process demonstrates the ADCs at 1 GS/s operation.

This paper proposes a synchronous digital LDO with adaptive clocking and dead-zone control without additional reference voltages. A test chip fabricated in a commercial 65 nm CMOS general-purpose (GP) process achieves 580x frequency modulation with 99.9% maximum efficiency at 0.6V supply.

This paper proposes an adaptive signal processing technique based on the equivalence of time resolution and quantization level. The time resolution means the resolution on time axis and the quantization level means the resolution on the value axis. We make a correlation between the time step size and the quantization step size to fix the product of them constant. Based on the correlation, we obtain an adaptive time resolution and quantization level signal expression. We confirm the efficiency of the proposed signal expression with respect to the data compression ratio and the error.