Low energy consumption and fault tolerance are often key objectives in the design of real-time embedded systems. However, these objectives are at odds, and there is a trade-off between them. Real-time systems usually use system level energy reduction methods, i.e., dynamic voltage scaling (DVS) and dynamic power management (DPM). Also hard real-time systems often use replication to achieve fault tolerance. In this paper, we investigate the impact of system level energy reduction methods on both the reliability and energy consumption of hard real-time systems which use replication for fault tolerance. In this analysis, we have considered four various existing energy management methods: 1) Classic DPM, 2) Classic DVS, 3) Postponement method: a variation of DPM which is only applicable to replicated systems, and 4) Hybrid method: a combination of Postponement and DVS. Based on the comparative study, we have provided guidelines so that a designer can decide which energy management method is more suitable for a given application. For example, we have shown that when reliability is the main concern, the postponement method is the most preferable. However, when the energy consumption is the primary concern, the hybrid method may be more appropriate.

This paper presents an efficient high-level synthesis (HLS) approach to improve RT-level concurrent testing. The proposed method used for both fault detection and fault location. At first the available resources are used in their dead intervals to test active resources for fault detection, and then some changes are applied to the RT-level controller to locate the faults. The fault detection step is based on a genetic algorithm (GA) search technique. This genetic algorithm is applied to the design after high level synthesis process to explore the test map. The proposed method has been evaluated based on dependability enhancement and area/latency overhead imposed to different benchmarks after applying our algorithm. The dependability has been considered in terms of fault coverage. The experimental result shows that applying our algorithm, the associated area overhead and performance penalty are negligible while the online fault coverage improvement is considerable.

The main approach of this paper is utilizing bio-inspired evolutionary strategies for high level test synthesis. In this paper a genetic algorithm (GA) is implemented to schedule a data-flow graph considering latency. Also, module binding is performed with another GA concurrently, considering resource constraints. The register allocation is performed using another GA which minimizes the number of registers. Then a co-evolutionary strategy merges the results of these three solutions, targeting testability improvement. Experimental results show using the proposed approach results in improvement in fault coverage with no or negligible overhead in area and delay.