When designing a pipelined digital system, delay buffers (often implemented as shift registers) are usually introduced into the system in order to synchronize the various signals impinging on each and every processing element. By thus insuring that all related inputs to each processing element arrive at precisely the same time, additional memory for this purpose need not be included within the processing elements themselves. The design of these elements may therefore be carried out independently of the topologies of the systems within which they will ultimately appear. Clearly, any solution to this synchronization problem is not likely to be unique; that is, there will usually exist many combinations of buffer locations and lengths that can produce overall input data synchronization in a typical pipelined network. When selecting one solution from many available solutions, it is natural to observe that it would be beneficial to implement a solution that makes use of the minimum number of total delay buffer stages necessary to produce synchronization in order that the system hardware cost and complexity may be reduced. In this paper, we present a technique to solve this delay buffer problem in polynomial time. Unlike other polynomial-time methods, this approach solves both the pipeline synchronization and buffer minimization problems within a single formulation. Furthermore, this technique is readily extended to handle pipelined systems containing feedback loops as well as processing elements whose fanout loads are greater than one. It has been used in a synthesis design environment.>

When designing a pipelined digital system, dekay buffers (often implemented as shifr registers) are usually introduced into the system in order to synchronize the various signals impinging on each processing element. That is, to insure that all inputs to a processing block arrive at precisely the same time. Automatic techniques for finding the lengths of such buffers, and their proper points of insertion in the system, have been proposed. They are usually bared on graph-theoretic approaches. [l-31. However, the solution to this synchronization problem is not Imique. so there exist many combinations of buffer locatim and length that can produce overall synchronization in a typical pipelined network. Obviously. it would be beneficial to determine the minimum number of total delay buffer stages necessary to s)mchronize a pipelined system, so that the system hardware cost and complexity can be reduced. In this paper. we present an algorithm to solve this buffer minimization problem. We will show that it can be recast in term of the clarsical minimum cost network flow problem. Hence, the time complexity of our algorithm is polynomial rather than exponential as for the algorithm reported in 141. Our technique is qplicable to system con%aining feedback Imps, but in the interest 4 brevity in this article we will treat only the most common case in which our wderlying system graphs are acyclic. The algorithm has been used in a silicon compiler design environment described in [SI.

The limitations on the numerical values of the functional arguments that are passed to the CORDIC computational units are discussed, with a special emphasis on the binary, fixed-point hardware implementation. Research in the area of expanding the allowed ranges of the input variables for which accurate output values can be obtained is presented. The methods proposed to expand the range of convergence for the CORDIC algorithm do not necessitate any unwidely overhead calculation, thus making this work amenable to a hardware implementation. The number of extra iterations introduced in the modified CORDIC algorithms is significantly less than the number of extra iterations discussed elsewhere. This reduction in the number of extra iterations will lead to a faster hardware implementation. Examples demonstrate the usefulness of the methods in realistic situations.>

C.S.G. Lee and P.R. Chang (1986) have shown how the mathematical and nonlinear function evaluation operations involved in the inverse kinematic solution for a six-joint manipulator could be re-expressed and reordered so as to allow their evaluation by an interconnection of CORDIC processors. The present authors describe the use of specialized, dedicated CORDIC processors, implemented in bit-serial form, to construct an inverse kinematics computational unit on a single VLSI chip.>

A useful class of digital filters is the rank order filter, of which the median filter is the most popular. This paper details the NMOS IC design of a 6-bit rank order filter based upon the approach of Fitch, Coyle, and Gallagher. The chip provides for programmable window lengths of 3, 5, 7, and 9; the selection of any element in the rank order; operation in the nonrecursive or recursive modes; and the ability to function in a "ganged" mode so that two or more identical chips can accommodate samples of length seven or eight bits.