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Demo Data from EDBT 2026 / reviewers in the wild / expert

Gerd Sandweg

dblp:93/3474 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 62% Integrated circuit design · 19% Electronic design automation · 19%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction set architecture		 0.011984
The Peripheral Processor PP4 - A Highly Regular VLSI Processor · ISCA 1984
Electronic design automation › physical design › VLSI layout
regular layout design		 0.011984
The Peripheral Processor PP4 - A Highly Regular VLSI Processor · ISCA 1984
Integrated circuit design
VLSI design		 0.011984
The Peripheral Processor PP4 - A Highly Regular VLSI Processor · ISCA 1984

Methods — techniques the papers use, named apart from their topics

automatic layout generation · 0.0NMOS fabrication · 0.0
YearPublicationVenuePosition
1984 The Peripheral Processor PP4 - A Highly Regular VLSI Processor
abstract
The architecture of an experimental 8/16-bit peripheral processor is described. The chip was fabricated in a 2-μm NMOS technology with two metal layers. There are about 300 000 transistors on a chip area of 105 mm2. The average time for a read-modify-write instruction is 200 ns. A highly modular and regular design style and some automatically generated layouts resulted in a short design time.
Wolf-Dietrich Moeller, Gerd Sandweg
 ISCA2