A VLIW (very long instruction word) architecture machine called the TRACE has been built along with its companion Trace Scheduling compacting compiler. This machine has three hardware configurations, capable of executing 7, 14, or 28 operations simultaneously. The 'seven-wide' achieves a performance improvement of a factor of five or six for a wide range of scientific code, compared to machines of higher cost and fast chip implementation technology (such as the VAX 8700). The TRACE extends some basic reduced-instruction-set computer (RISC) precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for run-time resource usage). The authors discuss the design of this machine and present some initial performance results.>

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACETM along with its companion Trace SchedulingTM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.

The system to be described processes the output of a 10th order LPC analyzer to obtain information characteristic of the four most prominent resonances in the LPC10 model spectra for voiced frames. Nonvoiced frames are specified by an LPC4 model. System operation for voiced frames depends upon the development of a set of reference clusters in the 4-dimensional spaces of resonance frequencies and spectral magnitudes; synthesis is performed with parallel resonators using the spectral representations for these clusters, with resonance bandwidths inserted according to rule. For nonvoiced frames clustering is done on log-area-ratios, with speech synthesized by a PARCOR filter. An extensive analysis of speech data was performed to obtain parameter quantization tables necessary for operation at rates from 1600 to 711 bits/sec. All critical computational processes have been demonstrated to operate in 16-bit arithmetic, and can be performed in real time on contemporary signal processing hardware.