A low-power SuperH/spl trade/ embedded processor core, the SH-X2, has been designed in 90-nm CMOS technology. The power consumption was reduced by using hierarchical fine-grained clock gating to reduce the power consumption of the flip-flops and clock-tree, synthesis and a layout that support implementation of the clock gating, and several-level power evaluations for RTL refinement. With this clock gating and RTL refinement, the power consumption of the clock-tree and flip-flops was reduced by 35% and 59%, including the process shrinking effects, respectively. As a result, the SH-X2 achieved 6,000 MIPS/W using a Renesas low-power process with lowered voltage. Its performance-power efficiency was 25% better than that of a 130-nm-process SH-X.

Describes the design methodology used for the architecture of the GMICRO/500 TRON CISC superscalar microprocessor. Its minimum performance goal is 50 MHz, 100 VAX-MIPS at 5 V. This severe goal and the CISC superscalar architecture make the design time long and require a lot of manpower and computer resources. The C language and Unix environment are used to reduce the cost of the logic simulation. Synopsis and GDT are used to accelerate the logic design and the cell/macro design. A supercomputer is used to shorten the gate-level simulation time. The total design manpower is under 603 man-months.>

The aliasing probabilities of multiple-input signature registers (MISR) with m inputs for a 2/sup m/-ary symmetric channel, where each of the (2/sup m/-1) possible errors is equally likely, are analyzed. For this error model, the aliasing probabilities of MISRs are analyzed using the weight distributions of maximum-distance-separable (MDS) codes. The results show that the aliasing probabilities over the 2/sup m/-ary symmetric channel do not depend on the polynomials that characterize the MISRs. That is, for the 2/sup m/-ary symmetric channel, the aliasing probability of an MISR based on a primitive polynomial is exactly the same as one based on a nonprimitive one. In addition, it is observed that the aliasing probabilities, P/sub al/ (n), as a function of test length n, are monotonous for error probabilities p=0.2, 0.4, and 0.8. The aliasing probabilities of multiple MISRs based on Reed-Solomon codes are analyzed again for the 2/sup m/-ary symmetric channel, using the weight distributions of Reed-Solomon codes, which are MDS codes.>