Hold timing closure and scan power are major concerns for any design. Hold closure for scan shift operation generally causes addition of buffers in the data path between flip-flops. This results in increased gate count that will toggle during the functional mode of operation thereby resulting in an increase in functional power. Scan operation also causes higher switching activity due to high toggling in a given test cycle. There are two components of power i.e. peak power and average power. Peak power increases IR-drop in the design, thereby reducing the voltage across the transistor and can lead to failure. In this paper we will present a modified flip-flop architecture that will serve two purposes i.e. enabling hold timing closure across process, voltage, temperature and reducing peak power during scan shift operation with minimal impact to functional timing and area. The modified flip-flop will introduce a half cycle delay in the data path invariant of process, voltage, temperature thereby easing hold closure. Test time and coverage are not impacted by the same. Existing ATPG tool generated pattern can be applied with this scheme. This approach reduces peak power close to 50% and reduces hold buffer area close to 40% in a given design.

Many software libraries (e.g., the Booch C++ Components, libg++, NIHCL, COOL) provide components (classes) that implement data structures. Each component is written by hand and represents a unique combination of features (e.g. concurrency, data structure, memory allocation algorithms) that distinguishes it from other components.We argue that this way of building data structure component libraries is inherently unscalable. Libraries should not enumerate complex components with numerous features; rather, libraries should take a minimalist approach: they should provide only primitive building blocks and be accompanied by generators that can combine these blocks to yield complex custom data structures.In this paper, we describe a prototype data structure generator and the building blocks that populate its library. We also present preliminary experimental results which suggest that this approach does not compromise programmer productivity nor the run-time performance of generated data structures.

We present a model of the data structure domain that is expressed in terms of the GenVoca domain modeling concepts [7]. We show how familiar data structures can be encapsulated as realms of plug-compatible, symmetric, and reusable components, and we show how complex data structures can be formed from their composition. The target application of our research is a precompiler for specifying and generating customized data structures.