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Christopher F. Joerg

dblp:93/4211 · DBLP profile ↗
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6ranked-venue papers
1as first author
0since 2021 · last 1998
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-authorArtificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1Graphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 60% Processor architecture and microarchitecture · 31% Interconnection networks and networks-on-chip · 9%
Software engineering, system software, and programming languages
1 paper
Runtime systems and virtual machines · 100%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Runtime systems and virtual machines › parallel runtime systems
multithreaded runtime
0.011995
Cilk: An Efficient Multithreaded Runtime System · PPoPP 1995
Parallel and multicore computing › task scheduling › dynamic scheduling
work-stealing scheduler
0.011995
Cilk: An Efficient Multithreaded Runtime System · PPoPP 1995
Parallel and multicore computing
load balancing
0.011995
Cilk: An Efficient Multithreaded Runtime System · PPoPP 1995
Interconnection networks and networks-on-chip
network interface
0.011992
A Tightly-Coupled Processor-Network Interface · ASPLOS 1992

Methods — techniques the papers use, named apart from their topics

critical path analysis · 0.0work-stealing · 0.0work stealing · 0.0
YearPublicationVenuePosition
1998 A recursive algorithm for the forced alignment of very long audio segments
abstract
In this paper we address the problem of aligning very long (of-ten more than one hour) audio files to their corresponding textual transcripts in an effective manner. We present an efficient recur-sive technique to solve this problem that works well even on noisy speech signals. The key idea of this algorithm is to turn the forced alignment problem into a recursive speech recognition problem with a gradually restricting dictionary and language model. The algorithm is tolerant to acoustic noise and errors or gaps in the text transcript or audio tracks. We report experimental results on a 3 hour audio file containing TV and radio broadcasts. We will show accurate alignments on speech under a variety of real acoustic conditions such as speech over music and speech over telephone lines. We also report re-sults when the same audio stream has been corrupted with white additive noise or compressed using a popular web encoding for-mat such as RealAudio. This algorithm has been used in our internal multimedia indexing project. It has processed more than 200 hours of audio from var-ied sources, such as WGBH NOVA documentaries and NPR web audio files. The system aligns speech media content in about one to five times realtime, depending on the acoustic conditions of the audio signal. 1.
Pedro J. Moreno 0001, Christopher F. Joerg, Jean-Manuel Van Thong, Oren Glickman
ICSLP2
1996 An Analysis of Dag-Consistent Distributed Shared-Memory Algorithms
abstract
In this paper, we analyze the performance of parallel mttltithreaded algorithms that use dag-consistent distributed shared memory.Specifically, we analyze execution time, page faults, and space requirements for multithreaded algorithms executed by a workstealing thread scheduler and the BACKER coherence algorithm for maintaining dag consistency.We prove that if the accesses to the backing store are random and independent (the BACKER algorithm actually uses hashing), then the expected execution time of a "fully strict" multithreaded computation on P processors, each with an LRU cache of C pages, is O(T1 (C)/P+ ntC7"), where T1(C) is the total work of the computation including page faults, L is its criticalpath length excluding page faults, and m is the minimum page transfer time.As a corollary to this theorem, we show that the expected number of page faults incurred by a computation executed on P pro-
Robert D. Blumofe, Matteo Frigo, Christopher F. Joerg, Charles E. Leiserson, Keith H. Randall
SPAA3
1996 Cilk: An Efficient Multithreaded Runtime System
abstract
Cilk (pronounced “silk”) is a C-based runtime system for multithreaded parallel programming. In this paper, we document the efficiency of the Cilk work-stealing scheduler, both empirically and analytically. We show that on real and synthetic applications, the “work” and “critical-path length” of a Cilk computation can be used to model performance accurately. Consequently, a Cilk programmer can focus on reducing the computation's work and critical-path length, insulated from load balancing and other runtime scheduling issues. We also prove that for the class of “fully strict” (well-structured) programs, the Cilk scheduler achieves space, time, and communication bounds all within a constant factor of optimal. The Cilk runtime system currently runs on the Connection Machine CM5 MPP, the Intel Paragon MPP, the Sun Sparcstation SMP, and the Cilk-NOW network of workstations. Applications written in Cilk include protein folding, graphic rendering, backtrack search, and the ★Socrates chess program, which won second prize in the 1995 ICCA World Computer Chess Championship.
Robert D. Blumofe, Christopher F. Joerg, Bradley C. Kuszmaul, Charles E. Leiserson, Keith H. Randall, Yuli Zhou
J. Parallel Distributed Comput.2
1995 Cilk: An Efficient Multithreaded Runtime System
abstract
Cilk (pronounced “silk”) is a C-based runtime system for multi-threaded parallel programming. In this paper, we document the efficiency of the Cilk work-stealing scheduler, both empirically and analytically. We show that on real and synthetic applications, the “work” and “critical path” of a Cilk computation can be used to accurately model performance. Consequently, a Cilk programmer can focus on reducing the work and critical path of his computation, insulated from load balancing and other runtime scheduling issues. We also prove that for the class of “fully strict” (well-structured) programs, the Cilk scheduler achieves space, time and communication bounds all within a constant factor of optimal.
Robert D. Blumofe, Christopher F. Joerg, Bradley C. Kuszmaul, Charles E. Leiserson, Keith H. Randall, Yuli Zhou
PPoPP2
1992 A Tightly-Coupled Processor-Network Interface
abstract
Article Free Access Share on A tightly-coupled processor-network interface Authors: Dana S. Henry View Profile , Christopher F. Joerg View Profile Authors Info & Claims ASPLOS V: Proceedings of the fifth international conference on Architectural support for programming languages and operating systemsSeptember 1992 Pages 111–122https://doi.org/10.1145/143365.143497Published:01 September 1992Publication History 80citation599DownloadsMetricsTotal Citations80Total Downloads599Last 12 Months34Last 6 weeks8 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF
Dana S. Henry, Christopher F. Joerg
ASPLOS2
1991 The Monsoon Interconnection Network
abstract
The interconnection network is described for Monsoon, a parallel processing dataflow computer. This network provides reliable, high bandwidth, low latency communication between the nodes of Monsoon. The major components of this network are two gate arrays: PaRC and the data link chip (DLC). PaRC (packet switched routing chip) is a CMOS gate array that implements a 4*4 packet routing switch that provides a high raw bandwidth (800 Mb/s) to each port. PaRC is designed so that much of this bandwidth can be utilized. The DLC is a high speed ECL gate array that reliably transfers data between boards.>
Christopher F. Joerg, G. Andrew Boughton
ICCD1