The need of a certification process for cloud-based services is emerging as a way to address some of the remaining obstacles facing the effective development and diffusion of the cloud-computing paradigm. In this paper we move the first steps towards a complete approach containing a conceptual framework where the specifications of basic, hybrid and incremental certification models for cloud-based services can be given. Specifically, we focus on the definition of a unifying meta-model to provide representational guidelines for (i) the definition of the security properties to be certified, (ii) the types of evidence underlying them, (iii) the phases of the certificate life cycle, as well as of all mechanisms for generating supporting evidence.

The design flow of a digital cryptographic device must take into account the evaluation of its security against attacks based on side channels observation. The adoption of high level countermeasures, as well as the verification of the feasibility of new attacks, presently require the execution of time-consuming physical measurements on the prototype product or the simulation at a low abstraction level. Starting from these assumptions, we developed an exploration approach centered on high level simulation, in order to evaluate the actual implementation of a cryptographic algorithm, being it software or hardware based. The simulation is performed within a unified tool based on SystemC, that can model a software implementation running on a microprocessor-based architecture or a dedicated hardware implementation as well as mixed software-hardware implementations with cycle-accurate resolution. Here we describe the tool and provide a large set of design explorations and characterizations based on actual implementations of the AES cryptographic algorithm, demonstrating how the execution of a large set of experiments allowed by the fast simulation engine can lead to important improvements in the knowledge and the identification of the weaknesses in cryptographic algorithm implementations.

The susceptibility of cryptographic devices to attacks based on power analysis can be both significantly and efficiently tested at early design steps. The results from a real case application show the advantages of the approach.

The threat of side-channel attacks (SCA) is of crucial importance when designing systems with cryptographic hardware or software. The FP6-funded project SCARD enhances the typical micro-chip design flow in order to provide a means for designing side-channel resistant circuits and systems. Appropriate SCA-simulation tools and SCA analysis for the designer of secure systems are part of the project goals. We consider these enhancements for traditional design flows of micro-chips as necessary in order to enable the design for the next generation of secure and dependable devices. SCARD is in its final phase, the final result a SCARD chip designed by using the developed design flow is currently implemented

A clock-controlled linear feedback shift register (LFSR) is a simple keystream generator consisting of an LFSR whose clock is controlled by another LFSR so that the output is an irregularly decimated LFSR sequence. Statistical distinguishers for keystream generators are algorithms whose objective is to distinguish the keystream sequence from a purely random sequence. Previously proposed statistical distinguishers for clock-controlled LFSRs are based on detecting binary linear relations in the keystream sequence that hold with a probability sufficiently different from one half. In this paper, a novel approach based on the correlation analysis of clock-controlled LFSRs is introduced. It significantly reduces the required computation time and essentially consists of a probabilistic reconstruction of bits in the regularly clocked LFSR sequence that satisfy the LFSR recurrence or any linear recurrence derived from low-weight multiples of the LFSR characteristic polynomial. The keystream sequence length and the computation time required for a reliable statistical distinction are analyzed both theoretically and experimentally. The new approach shows that there is no need to deal with the majority bits of blocks of LFSR bits as proposed recently. If individual bits or blocks of bits are considered instead, then the underlying probabilities can be computed theoretically instead of heuristically, which in turn allows a simple and general theoretical analysis of the keystream sequence length required

A probabilistic analysis is conducted to determine conditional and unconditional correlation weaknesses of cascades of up/down clocked shift registers. Similar results are also obtained for cascades of stop/go clocked shift registers. It is theoretically explained how to use the derived properties for fast correlation attacks, whose objective is to recover the linear feedback shift-register initial states, and the conditions for their success are obtained. The analysis and computations conducted indicate that the attacks are feasible in the practical case of relatively short cascades composed of long shift registers.