New technologies such as quantum-dot cellular automata (QCA) have been showing some remarkable characteristics that standard complementary-metal-oxide semiconductor (CMOS) in deep sub-micron cannot afford. Modeling systems and designing multiple-valued logic gates with QCA have advantages that facilitate the design of complicated logic circuits. In this paper, we propose a novel creative concept for quaternary QCA (QQCA). The concept has been set in QCASim, the new simulator developed by our team exclusively for QCAs’ quaternary mode. Proposed basic quaternary logic gates such as MIN, MAX, and different types of inverters (SQI, PQI, NQI, and IQI) have been designed and verified by QCASim. This study will exemplify how fast and accurately QCASim works by its handy set of CAD tools. A 1×4 decoder is presented using our proposed main gates. Preference points such as the minimum delay, area, and complexity have been achieved in this work. QQCA main logic gates are compared with quaternary gates based on carbon nanotube field-effect transistor (CNFET). The results show that the proposed design is more efficient in terms of latency and energy consumption.

Dynamic voltage and frequency scaling (DVFS) is a technique used to meet the power budget limitations in multi-core embedded systems. DVFS is applied to Networks-on-Chip (NoC) as a major contributor of the dissipated power on-chip. We propose an analytic model to accurately calculate the performance bounds on the best effort NoC with multiple voltage-frequency islands. The model supports dual-port buffer or handshaking mechanisms. We also suggest a method to set the frequencies of the islands to decrease the dissipated power. We examine our method and models and show their effectiveness.

Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM). This paper presents the design and simulation of a 16-bit x 32-bit SRAM with a new structure in QCA. Since QCA is a pipeline, this SRAM has a high operating speed. The 16-bit x 32-bit SRAM has a new structure with a 32-bit width designed and implemented in QCA. It has the ability of a conventional logic SRAM that can provide read/write operations frequently with minimum delay. The 16-bit x 32-bit SRAM is generalized and an n x 16-bit x 32-bit SRAM is implemented in QCA. Novel 16-bit decoders and multiplexers (MUXs) in QCA are presented that have been designed with a minimum number of majority gates and cells. The new SRAM, decoders, and MUXs are designed, implemented, and simulated in QCA using a signal distribution network to avoid the coplanar problem of crossing wires. The QCA-based SRAM cell was compared with the SRAM cell based on CMOS. Results show that the proposed SRAM is more efficient in terms of area, complexity, clock frequency, latency, throughput, and power consumption.

During the recent years, 2D mesh network-onchip has attracted much attention due to its suitability for VLSI implementation. The 2-dimensional de Bruijn topology for network-on-chip is introduced in this paper as an attractive alternative to the popular simple 2D mesh NoC. Its cost is equal to that of the simple 2D mesh but it has a logarithmic diameter. We compare the proposed network and the popular mesh network in terms of power consumption and network performance. Compared to the equal sized simple mesh NoC, the proposed de Bruijn-based network has better performance while consuming less energy.

In this paper, a 2D shuffle-exchange based mesh topology, or 2D SEM (shuffle-exchange mesh) for short, is presented for network-on-chips. The proposed two-dimensional topology applies the conventional well-known shuffle-exchange structure in each row and each column of the network. Compared to an equal sized mesh which is the most common topology in on-chip networks, the proposed shuffle-exchange based mesh network has smaller diameter but for an equal cost. Simulation results show that the 2D SEM effectively reduces the power consumption and improves performance metrics of the on-chip networks with regard to the conventional mesh topology.