The experimental results clearly show that the performance of ADSM scheme is limited by the communication of unnecessary data, while that of the UDSM scheme is limited by the instrumentation overhead. The UDSM scheme reduces transmission of unnecessary data and automatically prevents the severe false sharing at fetch-on-write, which is the problem in the page-based scheme.

On a large scale parallel computer system, shared memory provides a general and convenient programming environment. The paper describes a lightweight method for constructing an efficient shared memory system supported by hierarchical coherence management and generalized combining. The hierarchical management technique and generalized combining cooperate with each other. We eliminate the following heavyweight and high cost factors: a large amount of directory memory which is proportional to the number of processors, a separate memory component for the directory, tag/state information, and a protocol processor. In our method, the amount of memory required for the directory is proportional to the logarithm of the number of processors. This implies that a single word for each memory block is sufficient for covering a massively parallel system and that the access costs of the directory are small. Moreover, our combining technique, generalized combining, does not expect the accidental events which existing combining networks do, that is, events that messages meet each other at a switching node. A switching node can combine succeeding messages with a preceding one even after the preceding message leaves the node. This can increase the rate of successful combining. We have developed a prototype parallel computer OCHANOMIZ-5, that implements this lightweight distributed shared memory and generalized combining with simple hardware. The results of evaluating the prototype's performance using several programs show that our methodology provides the advantages of parallelization.

To execute a shared memory program efficiently, we have to manage memory consistency with low overheads, and have to utilize communication bandwidth of the platform as much as possible. A software distributed shared memory (DSM) can solve these problems via proper support by an optimizing compiler. The optimizing compiler can detect shared write operations, using interprocedural points-to analysis. It also coalesces shared write commitments onto contiguous regions, and removes redundant write commitments, using interprocedural redundancy elimination. A page based target software DSM system can utilize communication bandwidth, owing to coalescing optimization. We have implemented the above optimizing compiler and a run time software DSM on AP1000+. We have obtained a high speed-up ratio with the SPLASH-2 benchmark suite. The result shows that using an optimizing compiler to assist a software DSM is a promising approach to obtain a good performance. It also shows that the appropriate protocol selection at a write commitment is an effective optimization.

Article Free Access Share on Speculative execution model with duplication Authors: Kei Hiraki Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 Japan Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 JapanView Profile , Junji Tamatsukuri Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 Japan Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 JapanView Profile , Takashi Matsumoto Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 Japan Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 JapanView Profile Authors Info & Claims ICS '98: Proceedings of the 12th international conference on SupercomputingJuly 1998 Pages 321–328https://doi.org/10.1145/277830.277907Online:13 July 1998Publication History 5citation337DownloadsMetricsTotal Citations5Total Downloads337Last 12 Months3Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

We introduce a novel high-speed user-level communication and synchronization scheme "Memory-Based Communication Facilities (MBCF)" for a general-purpose system with an off-the-shelf communication-hardware.This mechanism is protected and virtualized as completely as memory so that it can be used not only in parallel systems but also in distributed systems.The MBCF realizes the direct remotememory-accesses in user-task-spaces and offers programmers and compilers a wide variety of functions and a large sharedmemory space.In this paper we first explain outlines and features of the MBCF, and present the high-speed implementation techniques for the MBCF.Then this paper describes varieties of the MBCF functions and introduces two novel memory-based mechanism: the Memory-Based FIFO and the Memory-Based Signal.Next we show that the MBCF is more flexible and less expensive than the messagepassing-style system-interfaces for communication or generalized active messages.Finally we show performance evaluations on the real MBCF implementation using lOOBASE-TX Ethernet.

Article Free Access Share on An I/O network architecture of the distributed shared-memory massively parallel computer JUMP-1 Authors: Hironori Nakajo Department of Computer and Systems Engineering, Kobe University Department of Computer and Systems Engineering, Kobe UniversityView Profile , Satoshi Ohtani Department of Computer and Systems Engineering, Kobe University Department of Computer and Systems Engineering, Kobe UniversityView Profile , Takashi Matsumoto Department of Information Science, The University of Tokyo Department of Information Science, The University of TokyoView Profile , Masadi Kohata Department of Information and Computer Engineering, Okayama University of Science Department of Information and Computer Engineering, Okayama University of ScienceView Profile , Kei Hiraki Department of Information Science, The University of Tokyo Department of Information Science, The University of TokyoView Profile , Yukio Kaneda Department of Computer and Systems Engineering, Kobe University Department of Computer and Systems Engineering, Kobe UniversityView Profile Authors Info & Claims ICS '97: Proceedings of the 11th international conference on SupercomputingJuly 1997 Pages 253–260https://doi.org/10.1145/263580.263645Published:11 July 1997Publication History 4citation247DownloadsMetricsTotal Citations4Total Downloads247Last 12 Months2Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

In multiprocessor systems, overheads caused by interprocessor communication and synchronization have been one of the largest obstacles for efficient execution of parallel programs. To reduce these overheads in shared-memory/shared-bus multiprocessors, we have proposed two hardware mechanisms: the Inter-Cache Snoop Control Mechanism (ICSCM), which dynamically switches snoop-protocols for improving shared-bus utilization, and the Mechanism for Integrated Synchronization and Communication (MISC), which extends ICSCM to support producer-consumer type synchronization efficiently. We have developed an execution-driven multiprocessor simulator for evaluating performance with these mechanisms. Simulation experiments on doacross loops show remarkable speed-ups by ICSCM/MISC mechanisms. Although the proposed mechanisms are originally implemented on a single shared-bus system, they are easily applicable to a clustered multiprocessing systems. The methods used in a clustered system are discussed.