EDBT 2026 Demo / reviewers in the wild / expert
Chris Gianos
dblp:93/4391
· DBLP profile ↗
3ranked-venue papers
1as first author
1since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 91% Cloud and datacenter computing · 9% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › cache management
cache allocation |
0.2 | 1 | 2016 | Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family · HPCA 2016 |
Memory systems
cache management |
0.2 | 1 | 2016 | Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family · HPCA 2016 |
Memory systems › cache management
cache monitoring |
0.2 | 1 | 2016 | Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family · HPCA 2016 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | Architecting for Flexibility and Value with Next Gen Intel® Xeon® ProcessorsabstractContinuing demand for CPU cores that deliver high performance per core Chris Gianos |
HCS | 1 |
| 2016 | Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product familyabstractOver the last decade, addressing quality of service (QoS) in multi-core server platforms has been growing research topic. QoS techniques have been proposed to address the shared resource contention between co-running applications or virtual machines in servers and thereby provide better isolation, performance determinism and potentially improve overall throughput. One of the most important shared resources is cache space. Most proposals for addressing shared cache contention are based on simulations and analysis and no commercial platforms were available that integrated such techniques and provided a practical solution. In this paper, we will present the first set of shared cache QoS techniques designed and implemented in state-of-the-art commercial servers (the Intel® Xeon® processor E5-2600 v3 product family). We will describe two key technologies: (i) Cache Monitoring Technology (CMT) to enable monitoring of shared cache usage by different applications and (ii) Cache Allocation Technology (CAT) which enables redistribution of shared cache space between applications to address contention. This is the first paper to describing these techniques as they moved from concept to reality, starting from early research to product implementation. We will also present case studies highlighting the value of these techniques using example scenarios of multi-programmed workloads, virtualized platforms in datacenters and communications platforms. Finally, we will describe initial software infrastructure and enabling for industry practitioners and researchers to take advantage of these technologies for their QoS needs. Andrew Herdrich, Edwin Verplanke, Priya Autee, Ramesh Illikkal, Chris Gianos, Ronak Singhal, Ravi R. Iyer 0001 |
HPCA | 5 |
| 2015 | Intel® Xeon® Processor D: The First Xeon processor optimized for dense solutions
Dheemanth Nagaraj, Chris Gianos |
Hot Chips Symposium | 2 |