Demo Data from EDBT 2026 / reviewers in the wild / expert
Narsingh Deo
dblp:93/4704
· DBLP profile ↗
40ranked-venue papers
17as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 18 · 8 first-authorTheory of computation · 12 · 5 first-authorDatabases, data management, data science and information retrieval · 8 · 4 first-authorComputer networks · 3 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 3 · 1 first-authorArtificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
6 papers |
Performance modeling and evaluation · 32% Electronic design automation · 29% Parallel and multicore computing · 21% | |
| Theoretical computer science
4 papers |
Algorithms and data structures · 33% Graph algorithms and graph theory · 32% Mathematical optimization · 27% |
Topics — the 20 heaviest of 22, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › parallel algorithms › parallel string algorithms
parallel parsing |
0.0 | 1 | 1990 | Estimating the Speedup in Parallel Parsing · IEEE Trans. Software Eng. 1990 |
Performance modeling and evaluation › performance prediction
speedup estimation |
0.0 | 1 | 1990 | Estimating the Speedup in Parallel Parsing · IEEE Trans. Software Eng. 1990 |
Electronic design automation › physical design › VLSI layout
gate matrix layout |
0.0 | 1 | 1987 | Exact and Approximate Solutions for the Gate Matrix Layout Problem · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation
physical design |
0.0 | 1 | 1987 | Exact and Approximate Solutions for the Gate Matrix Layout Problem · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Algorithms and data structures
dynamic programming |
0.0 | 1 | 1987 | Exact and Approximate Solutions for the Gate Matrix Layout Problem · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Mathematical optimization › optimization
layout optimization |
0.0 | 1 | 1987 | Exact and Approximate Solutions for the Gate Matrix Layout Problem · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Performance modeling and evaluation
analytical modeling |
0.0 | 1 | 1990 | Estimating the Speedup in Parallel Parsing · IEEE Trans. Software Eng. 1990 |
Memory systems
memory hierarchy |
0.0 | 1 | 1979 | Interference in Multiprocessor Systems with Localized Memory Access Probabilities · IEEE Trans. Computers 1979 |
Memory systems
memory interference |
0.0 | 1 | 1979 | Interference in Multiprocessor Systems with Localized Memory Access Probabilities · IEEE Trans. Computers 1979 |
Memory systems › memory interference
multiprocessor memory interference |
0.0 | 1 | 1979 | Interference in Multiprocessor Systems with Localized Memory Access Probabilities · IEEE Trans. Computers 1979 |
Performance modeling and evaluation
workload characterization |
0.0 | 1 | 1979 | Interference in Multiprocessor Systems with Localized Memory Access Probabilities · IEEE Trans. Computers 1979 |
Graph algorithms and graph theory › graph theory › graph transformation
graph modification |
0.0 | 1 | 1979 | Node-Deletion NP-Complete Problems · SIAM J. Comput. 1979 |
Graph algorithms and graph theory › graph theory › graph transformation › graph modification
vertex deletion |
0.0 | 1 | 1979 | Node-Deletion NP-Complete Problems · SIAM J. Comput. 1979 |
Graph algorithms and graph theory
graph theory |
0.0 | 1 | 1976 | On Algorithms for Enumerating All Circuits of a Graph · SIAM J. Comput. 1976 |
Graph algorithms and graph theory › planar graphs
planarity testing |
0.0 | 1 | 1976 | Note on Hopcroft and Tarjan's Planarity Algorithm · J. ACM 1976 |
Electronic design automation › hardware verification and test
fault modeling |
0.0 | 1 | 1969 | Author's Reply3 · IEEE Trans. Computers 1969 |
Hardware reliability and fault tolerance › redundancy
modular redundancy |
0.0 | 1 | 1968 | Generalized Parallel Redundancy in Digital Computers · IEEE Trans. Computers 1968 |
Hardware reliability and fault tolerance
redundancy |
0.0 | 1 | 1968 | Generalized Parallel Redundancy in Digital Computers · IEEE Trans. Computers 1968 |
Graph algorithms and graph theory
graph algorithms |
0.0 | 1 | 1976 | Note on Hopcroft and Tarjan's Planarity Algorithm · J. ACM 1976 |
Hardware reliability and fault tolerance › system diagnosis
self-diagnosis |
0.0 | 1 | 1966 | The Self-Diagnosability of a Computer · IEEE Trans. Electron. Comput. 1966 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0heuristic algorithm · 0.0dynamic programming · 0.0analytical modeling · 0.0vector space method · 0.0polynomial reduction · 0.0markov chain analysis · 0.0combinatorial bounds · 0.0reliability modeling · 0.0probability density function analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | A theorem proving approach for automatically synthesizing visualizations of flow cytometry dataabstractBACKGROUND: Polychromatic flow cytometry is a popular technique that has wide usage in the medical sciences, especially for studying phenotypic properties of cells. The high-dimensionality of data generated by flow cytometry usually makes it difficult to visualize. The naive solution of simply plotting two-dimensional graphs for every combination of observables becomes impractical as the number of dimensions increases. A natural solution is to project the data from the original high dimensional space to a lower dimensional space while approximately preserving the overall relationship between the data points. The expert can then easily visualize and analyze this low-dimensional embedding of the original dataset. RESULTS: This paper describes a new method, SANJAY, for visualizing high-dimensional flow cytometry datasets. This technique uses a decision procedure to automatically synthesize two-dimensional and three-dimensional projections of the original high-dimensional data while trying to minimize distortion. We compare SANJAY to the popular multidimensional scaling (MDS) approach for visualization of small data sets drawn from a representative set of benchmarks, and our experiments show that SANJAY produces distortions that are 1.44 to 4.15 times smaller than those caused due to MDS. Our experimental results show that SANJAY also outperforms the Random Projections technique in terms of the distortions in the projections. CONCLUSIONS: We describe a new algorithmic technique that uses a symbolic decision procedure to automatically synthesize low-dimensional projections of flow cytometry data that typically have a high number of dimensions. Our algorithm is the first application, to our knowledge, of using automated theorem proving for automatically generating highly-accurate, low-dimensional visualizations of high-dimensional data. Sunny Raj, Faraz Hussain 0001, Zubir Husein, Neslisah Torosdagli, Damla Turgut, Narsingh Deo, Sumanta N. Pattanaik, Chung-Che Jeff Chang, Sumit Kumar Jha 0001 |
BMC Bioinform. | 6 |
| 2008 | Techniques for analyzing dynamic random graph models of web-like networks: An overviewabstractAbstract Various random graph models have recently been proposed to replicate and explain the topology of large, complex, real‐life networks such as the World Wide Web and the Internet. These models are surveyed in this article. Our focus has primarily been on dynamic random graph models that attempt to account for the observed statistical properties of web‐like networks through certain dynamic processes guided by simple stochastic rules. Particular attention is paid to the equivalence between mathematical definitions of dynamic random graphs in terms of inductively defined probability spaces and algorithmic definitions of such models in terms of recursive procedures. Several techniques that have been employed for studying dynamic random graphs—both heuristic and analytic—are expounded. Each technique is illustrated through its application in analyzing various graph parameters, such as degree distribution, degree‐correlation between adjacent nodes, clustering coefficient, distribution of node‐pair distances, and connected‐component size. A discussion of the most recent salient work and a comprehensive list of references in this rapidly‐expanding area are included. © 2007 Wiley Periodicals, Inc. NETWORKS, 2008 Aurel Cami, Narsingh Deo |
Networks | 2 |
| 2007 | Exploring Topological Properties of NMR GraphsabstractIn this paper we explore the topological properties of graphs derived from nuclear magnetic resonance (NMR) restraint data. Only the distance bound data is considered, connecting nodes only if the file contains a bound for the corresponding inter-atomic distance. Since NMR provides bounds for spatially-close atom pairs, the structure of the NMR graph depends heavily on the molecule's 3D shape. Therefore, understanding NMR graph topology is relevant to 3D structure prediction. We examine NMR graphs for nine molecules, sizes ranging between 195 and 1178 nodes. Three categories of topological properties are studied: connected components, diameter, and node-degree sequence. Several interesting observations emerged when relating the diameter and maximum degree to the size of the graph. Paulius Micikevicius, Narsingh Deo |
BIBE | 2 |
| 2007 | Preferential deletion in dynamic models of web-like networks
Narsingh Deo, Aurel Cami |
Inf. Process. Lett. | 1 |
| 2005 | A Graph Theoretic Algorithm for Placing Data and Parity to Tolerate Two Disk Failures in Disk Array SystemsabstractIn recent years commercial redundant arrays of inexpensive disks (RAID) systems have become increasingly popular because of their enhanced I/O bandwidths, large capacities and low cost. However, the continued demand for larger capacities at low cost, has led to the use of larger arrays with increased probability of random disk failures. Hence the need for RAID systems to tolerate two or more random disk failures without sacrificing performance or storage space. In this paper, we devise a novel graph-theoretic method for placing data and parity in an array of N disks (N /spl ges/ 3) to enable its recovery from any two random disk failures. We first provide an algorithm for the case when the number of disks N = P - 1, where P is a prime number, and then generalize the solution for any arbitrary N. We also determine the fraction of space used for storing parity in an array of N disks employing our algorithm, and show that this fraction has the optimal value of 21N for all N = P - 1. For illustration, this fraction and the percentage of its difference from the optimal ratio are graphed for values of N between 5 and 255. Finally, we describe a method for determining the data-blocks from where the reconstruction of two failed disks can be started in such an array. Narsingh Deo, Sanjeeb Nanda |
IV | 1 |
| 2005 | Cluster Computing for Determining Three-Dimensional Protein Structure
Paulius Micikevicius, Narsingh Deo |
J. Supercomput. | 2 |
| 2004 | Graph compression and the zeros of polynomials
Bruce E. Litow, Narsingh Deo |
Inf. Process. Lett. | 2 |
| 2000 | Computing a Diameter-Constrained Minimum Spanning Tree in Parallel
Narsingh Deo, Ayman M. Abdalla |
CIAC | 1 |
| 1999 | Memory-Efficient Enumeration of Constrained Spanning Trees
Jürg Nievergelt, Narsingh Deo, Ambros Marzetta |
Inf. Process. Lett. | 2 |
| 1998 | Parallel Dictionaries Using AVL Trees
Muralidhar Medidi, Narsingh Deo |
J. Parallel Distributed Comput. | 2 |
| 1996 | Incorporating Latent Semantic Indexing into a Neural Network Model for Information RetrievalabstractWe incorporate the Latent Semantic Indexing (LSl) technique into a competition-based neural network model for information retrieval.The original neural network model was based on a causal inference network, incorporating Roget's Thesaurus, that connects the index terms and related documents.Since the pmcIess of creating or updating a thesaurus is rather expensive, we apply the LSI technique to provide an automated procedure that captures the semantic relationship between the doctrments and index terms.C)ur experimental results using four standard text collections show that the LSI-baaed model generates appreciable improvement in retrieval effectiveness with faster query evaluation over the thesatrrus-ba~sed model. Inien Syu, Sheau-Dong Lang, Narsingh Deo |
CIKM | 3 |
| 1996 | Minimum-Weight Degree-Constrained Spanning Tree Problem: Heuristics and Implementation on an SIMD Parallel Machine
Bruce Boldon, Narsingh Deo, Nishit Kumar |
Parallel Comput. | 2 |
| 1995 | Metric Graphs Elastically Embeddable in the Plane
Jürg Nievergelt, Narsingh Deo |
Inf. Process. Lett. | 2 |
| 1994 | An Optimal Parallel Algorithm for Merging Using Multiselection
Narsingh Deo, Muralidhar Medidi |
Inf. Process. Lett. | 1 |
| 1994 | Parallel Construction of (a, b) -Trees
Narsingh Deo, Muralidhar Medidi |
J. Parallel Distributed Comput. | 1 |
| 1992 | Constructing Height-Balanced Trees in Parallel
Narsingh Deo, Muralidhar Medidi |
ICPP (3) | 1 |
| 1992 | Stirling Networks: A Versatile Combinatorial Topology for Multiprocessor Systems
Sajal K. Das 0001, Joydeep Ghosh, Narsingh Deo |
Discret. Appl. Math. | 3 |
| 1992 | Parallel heap: An optimal parallel priority queue
Narsingh Deo, Sushil K. Prasad |
J. Supercomput. | 1 |
| 1991 | Parallel algorithms for merging and sorting
Narsingh Deo, Dilip Sarkar |
Inf. Sci. | 1 |
| 1990 | Parallel Heap
Narsingh Deo, Sushil K. Prasad |
ICPP (3) | 1 |
| 1990 | Two minimum spanning forest algorithms on fixed-size hypercube computers
Sajal K. Das 0001, Narsingh Deo, Sushil K. Prasad |
Parallel Comput. | 2 |
| 1990 | Parallel graph algorithms for hypercube computers
Sajal K. Das 0001, Narsingh Deo, Sushil K. Prasad |
Parallel Comput. | 2 |
| 1990 | Estimating the Speedup in Parallel ParsingabstractA method for estimating the speedup for asynchronous bottom-up parallel parsing is presented. Two models for bottom-up parallel parsing are proposed, and the speedup for each of the two models is estimated. The speedup obtained for model A is a very close to the simulation result already available in literature; however, the model is restrictive because it can only communicate with its immediate left and right neighbors. This increases the processor coordination and interprocessor communication times. Model B, while showing a greater speedup time, is expensive to construct when the number of processors is large.> Dilip Sarkar, Narsingh Deo |
IEEE Trans. Software Eng. | 2 |
| 1989 | Gate Matrix Layout Revisited: Algorithmic Performance and Probabilistic Analysis
Sajal K. Das 0001, Narsingh Deo, Sushil K. Prasad |
FSTTCS | 2 |
| 1988 | Parallel algorithms and architectures report of a workshop
Duncan A. Buell, David A. Carlson, Yuan-Chieh Chow, Karel Culík, Narsingh Deo, Raphael A. Finkel, Elias N. Houstis, Elaine M. Jacob Son, Zvi M. Kedem, Janusz S. Kowalik, Philip Kuekes, Joanne L. Martin, George A. Michael, Neil S. Ostlund, Jerry Potter, D. K. Pradhan, Michael J. Quinn, G. W. Stewart, Quentin F. Stout, Layne T. Watson |
J. Supercomput. | 5 |
| 1987 | An Optimal Parallel Parsing Algorithm for a Class of Block Structured Languages
Dilip Sarkar, Narsingh Deo |
ICPP | 2 |
| 1987 | Parallel Algorithms for Parenthesis Matching and Generation of Random Balanced Sequences of Parentheses
Dilip Sarkar, Narsingh Deo |
ICS | 2 |
| 1987 | Exact and Approximate Solutions for the Gate Matrix Layout ProblemabstractWe consider the gate matrix layout problem for VLSI circuits, which is known to be NP-complete. We present an efficient algorithm for determining whether two tracks suffice. For the general problem of minimizing the number of tracks (and, hence, the area) needed, we design an attractive dynamic programming formulation to guarantee optimality. We also investigate the performance of fast heuristic algorithms published in the literature and demonstrate that there exist families of problem instances for which the ratio of the number of tracks required by these heuristics to the optimal value is unbounded. Moreover, we show that this result holds for any on-line layout algorithm. We additionally prove that, unless P = NP, no polynomial-time layout algorithm can ensure that the number of tracks it requires never exceeds k plus the optimum, for any constant k. Narsingh Deo, Mukkai S. Krishnamoorthy, Michael A. Langston |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1986 | Estimating the Speedup in Parallel Parsing
Dilip Sarkar, Narsingh Deo |
ICPP | 2 |
| 1984 | Shortest-path algorithms: Taxonomy and annotationabstractAbstract We have evolved a classification scheme to characterize algorithms for solving shortestpath problems. The algorithms are classified according to (A) the problem type, i.e., the question being asked about the given network; (B) the input type, i.e., the salient features of the given network which impact on the design of the algorithm and selection of data structures; and (C) the type of underlying technique employed to solve the problem. An annotated bibliography of 79 selected references on shortest‐path algorithms is included. We have also provided a more complete listing of 222 references carefully culled out of a larger body of literature on shortest‐path algorithms through the year 1979. Narsingh Deo, Chi-Yin Pang |
Networks | 1 |
| 1982 | Algorithms for Generating Fundamental Cycles in a GraphabstractThe following problem is considered: Given an undirected, connected graph G, find a spanning tree in G such that the sum of the lengths of the fundamental cycles (with respect to this tree) is minimum.This problem, besides being interesting in its own right, is useful in a variety of situations It is shown that this problem is NP-complete.A number of polynomial-time, heuristic algorithms which yield "good" suboptimal solutions are presented and their performances are discussed.Finally, it is shown that for regular graphs of order n the expected value of the total length of a minimum fundamentalcycle set does not exceed O(n2). Narsingh Deo, G. M. Prabhu, Mukkai S. Krishnamoorthy |
ACM Trans. Math. Softw. | 1 |
| 1979 | Complexity of the minimum-dummy-activities problem in a pert networkabstractAbstract Any complex project consists of a number of activities which are carried out in some specified precedence order. One of the factors that is considered is in minimizing the project completior, time. The computation of the optimum project completion time is proportional to the number of edges, including dummy activities. In the past, many algorithms were proposed to yield minimum number of dummy activities required to satisfy the given precedence relation. In this paper we transform the node‐cover problem in graphs of degree at most 3 to the minimum‐dummy‐activities problem. Using this transformation we show that the minimum‐dummy‐activities problem in a PERT network is NP‐complete. The significance of this result is that it is worthwhile in developing a polynomial time heuristic algorithm for solving the dummy activities problem. Mukkai S. Krishnamoorthy, Narsingh Deo |
Networks | 2 |
| 1979 | Node-Deletion NP-Complete ProblemsabstractThe entire class of node-deletion problems can be stated as follows: Given a graph G, find the minimum number of nodes to be deleted so that the remaining subgraph g satisfies a specified property $\pi $. For each $\pi $, a distinct node-deletion problem arises. The various deletion problems considered here are for the following properties: each component of g is (i) null, (ii) complete, (iii) a tree, (iv) nonseparable, (v) planar, (vi) acyclic, (vii) bipartite, (viii) transitive, (ix) Hamiltonian, (x) outerplanar, (xi) degree-constrained, (xii) line invertible, (xiii) without cycles of a specified length, (xiv) with a singleton K-basis, (xv) transitively orientable, (xvi) chordal, and (xvii) interval. In this paper, these 17 different node-deletion problems are shown to be NP-complete. A unified approach is taken for the transformations employed in the proofs. Mukkai S. Krishnamoorthy, Narsingh Deo |
SIAM J. Comput. | 2 |
| 1979 | Interference in Multiprocessor Systems with Localized Memory Access ProbabilitiesabstractPast studies of memory interference in multiprocessor systems have generally assumed that the references of each processor are uniformly distributed among the memory modules. In this paper we develop a model with local referencing, which reflects more closely the behavior of real-life programs. This model is analyzed using Markov chain techniques and expressions are derived for the multiprocessor performance. New expressions are also obtained for the performance in the traditional uniform reference model and are compared with other expressions-available in the literature. Results of a simulation study are given to show the accuracy of the expressions for both models. Adarshpal S. Sethi, Narsingh Deo |
IEEE Trans. Computers | 2 |
| 1977 | Generalizations of Line Graphs and Applications
Narsingh Deo, Mukkai S. Krishnamoorthy, Ajit B. Pai |
Inf. Process. Lett. | 1 |
| 1976 | Note on Hopcroft and Tarjan's Planarity AlgorithmabstractErrata are given for “Efficient Planarity Testing” by John Hopcroft and Robert Tarjan [ J. ACM 21 , 4 (Oct. 1974), 549-568]. Narsingh Deo |
J. ACM | 1 |
| 1976 | On Algorithms for Enumerating All Circuits of a GraphabstractA brief description and comparison of all known algorithms for enumerating all circuits of a graph is provided, and upper bounds on computation time of many algorithms are derived. The vector space method of circuit enumeration is discussed. It is proved that $K_3 ,K_4 ,K_4 - x$ and $K_{3,3} $ are the only undirected and reduced graphs which do not have any edge-disjoint unions of circuits. Prabhaker Mateti, Narsingh Deo |
SIAM J. Comput. | 2 |
| 1969 | Author's Reply3abstractIn general, when a logical element fails it can fail not only at true or false levels but at any one of infinitely many different voltage levels. Thus, strictly speaking, one should talk of probability density function, rather than discrete probabilities. When considering the simultaneous failures of several modules one has to consider the joint probability density function. Narsingh Deo |
IEEE Trans. Computers | 1 |
| 1968 | Generalized Parallel Redundancy in Digital ComputersabstractAbstract—Triple modular redundancy becomes common when applications place a high premium on the reliability of a digital computer . As the weight, volume, and cost of electronic components decrease, 5-, 7-, or 9-fold redundancies should be considered. This short note presents expressions on the reliabilities of a general n-fold redundant system. Narsingh Deo |
IEEE Trans. Computers | 1 |
| 1966 | The Self-Diagnosability of a ComputerabstractMaximum capability for self-diagnosis with minimum additional hardware is the goal of every designer of a general purpose computer today. A yardstick with which the self-diagnosability of a system can be measured is proposed. Narsingh Deo |
IEEE Trans. Electron. Comput. | 1 |