A grid refinement methodology suitable for arbitrary spatial dimensions and geometries is developed. Using just the structural description of a device-specified by the user or taken directly from the output of a process simulator-strategies for creating an initial grid are proposed, embodying whatever knowledge the simulator can have about how the solution will behave. After solving the PDEs, a grid is adapted by examining the local error involved in the discretization process. A set of procedures is proposed for this purpose and shown to be nearly optimal in terms of cost and efficiency. The key to implementing a robust and efficient scheme lies in the choice of a suitable error indicator; it is shown that some of the more obvious candidates can perform quite poorly. The initial grid construction and error indicator schemes are used to show how the full adaptation procedure works on some practical examples.>

An efficient self-consistent device simulator coupling Poisson equation and Monte Carlo transport suitable for general silicon devices, including those with regions of high doping/carrier densities, is discussed. Key features include an original iteration scheme and an almost complete vectorization of the program. The simulator has been used to characterize nonequilibrium effects in deep submicron nMOSFETs. Substantial overshoot effects are noticeable at gate lengths of 0.25 mu m at room temperatures.>

Robust computational techniques are presented for steady-state characterization of CMOS latchup via numerical device simulation. Of specific interest are efficient means of accurately evaluating knees in I-V characteristics, corresponding to latchup triggering and holding points. Making use of predictor-corrector continuation procedures and special initial-guess strategies, more than an order of magnitude improvement in computational efficiency is achieved over previous approaches. It is shown that for some latchup problems, these methods are essential due to their unique ability to trace characteristics that are multivalued in both I and V. Simulated results for both triggering and holding characteristics of a VLSI CMOS process are presented, from which primary structural dependencies are identified and new physical insight is obtained.>

In order to analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree well. The causes of short-channel effects have been understood and explained by the simulations. Two-dimensional effects and velocity saturation are the main causes of short-channel effects in MOS transistor capacitances. Two-dimensional simulation was found to be a useful tool for studying mobility models, as well as for obtaining capacitance models for circuit simulation.

Computer-aided analysis of integrated circuit devices has played a critical role for more than three decades of technology evolution. In the 1950s and early 1960s simulation was used extensively to characterize the operating principles of both bipolar and MOS devices. Bipolar effects such as base-width modulation and base pushout were characterized as well as MOS phenomena including gradual channel and channel-length modulation effects. During the late 1960s and throughout the 1970s simulation provided critical insight in the scaling of devices leading to the advent of very large scale integration (VLSI). Starting in the mid-1970s the modeling of fabrication technology became an important adjunct to device analysis. The need to control threshold and subthreshold behavior of scaled devices played a significant role in this synergistic coupling. Now in the mid-1980s the role of both device and process analysis have each come to new plateaus of both performance and utility. The scaling of submicrometer channel-length MOS devices poses a new set of constraints and challenges. This paper traces the evolution of computer-aided analysis over the past three decades. Unique aspects of the device physics and the role of device and process analysis at each phase of development will be presented. The progression from device conception towards stabilizing the technologies for large-scale product are presented. Problems of submicrometer technology including both production issues as well as new physical requirements for both process and device modeling will be dealt with, including the opportunity presented with the rapid advances in computer technology and the seemingly inevitable computational bottleneck posed by the growing needs for three-dimensional simulation.

This paper examines iterative methods for solving the semiconductor device equations. The emphasis is on fully coupled methods, because of the failure of decoupled methods for on-state devices. Using the PISCES-II device simulator as a vehicle, incomplete factorization and operator decomposition iterative methods are presented for solving the Newton equations. The dependencies of these methods on factors such as choice of variables, bias condition and initial guess are analyzed. The results are compared with sparse Gaussian elimination.

The latchup behavior of a VLSI CMOS technology using hybrid Schottky-ohmic contact sources and drains and a high resistivity substrate has been extensively studied via two dimensional numerical simulation. The modeling allows quantitative explanation of the triggering and sustaining behavior of such structures, as well as an accurate characterization of the influence of the various process and geometrical parameters on the resistance to latchup. The technology is compared to a corresponding low resistivity substrate (epi) CMOS technology.