The accuracy and precision of time synchronization in Ethernet must be enhanced since Ethernet is becoming a critical component of telecommunication networks. This paper investigates a precise time synchronization technique that supports Gb/s Ethernet. To obtain accurate time synchronization, delay variation in message transfer and processing must be minimized. For this purpose, the paper first describes an implementation of preemptive priority queuing, which decreases the message delay variation of Ethernet. The paper then proposes a time synchronization method that is performed in the lower protocol layer and then describes its implementation on FPGA-based hardware. The proposed method achieves superior time accuracy and precision through the low message transfer/processing delay variation provided by preemptive priority, lower layer execution, and hardware implementation. The effectiveness of the method is confirmed through experiments.

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8*8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s.>

The authors propose and describe an original feedback banyan switching network topology and control algorithm. This feedback banyan network prevents congestion even at high throughput. It does so by establishing a feedback route for the output packets from the output port to the input port of the banyan switching network. Input accommodated logical channels that do not encounter congestion within the switching network are output directly from the intended output port. Other packets are returned to the input port via the feedback route, then rerouted.>