Demo Data from EDBT 2026 / reviewers in the wild / expert
Jim Kupec
dblp:93/5211
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 81% Integrated circuit design · 19% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
analog and mixed-signal circuits |
0.0 | 1 | 2006 | How will the fabless model survive? · DAC 2006 |
Electronic design automation › design methodology
design flows and tools |
0.0 | 1 | 2006 | How will the fabless model survive? · DAC 2006 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | How will the fabless model survive?abstractThe fabless model was traditionally enabled through clean interfaces - both in technical and business terms - between foundries and fabless semiconductor companies. However, with advanced geometry and analog/mixed-signal process nodes, the technical challenges have been greatly magnified, so that successful semiconductor design requires intimate co-optimization of design and manufacturing, infringing upon those clean interfaces. The panel presents views to these challenges and specifically how companies are planning to address them. Thomas Hartung, Jim Kupec, Ana Hunter, Brad Paulsen, Felicia James, Nick Yu |
DAC | 2 |