The security closure of integrated circuits (ICs) is an emerging area of research within the very large scale integration (VLSI) community. Malicious third parties, referred to as “attackers,” can employ various techniques to leak, alter, or manipulate the logic of a circuit. When targeting a completed layout, their primary goal is often the insertion of hardware trojans. In this work, we present algorithms that strengthen placement solutions against hardware trojan attacks. While state-of-the-art methods rely on exhaustive placement algorithms, we propose a clustering-based placement approach that reduces the number of moved cells by up to 17%. Additionally, we introduce a cell movement heuristic aimed at preventing increases in wirelength. Our methods reduce vulnerable placement sites by up to 78% while maintaining minimal impact on design performance. Compared to other approaches, our solution decreases the amount of moved cells to an average of 8%, mitigating the impact on wirelength to an average of 0.5%.

The semiconductor industry faces growing difficulties in addressing technical and technological challenges, such as the exhaustion of CMOS downscaling and the limitations imposed by the von Neumann bottleneck. At the same time, this sector needs to meet the requirements of increasingly demanding applications, such as Internet of Things (IoT) and Artificial Intelligence (AI). These circumstances have boosted the research development related to emerging technologies and new computing paradigms. In this context, the unique features of memristive devices make them promising objects of study in both areas. In light of this, we present a new concept for performing logic-in-memory (LiM) using memristive devices. Our method is based on expressions in the form of sum-of-products (SOP), and it establishes a pattern of voltage application on memristors, from which it is possible to compute any Boolean function through sequential steps. Our proposal exhibits an intuitive relationship with logic synthesis tools currently used in digital circuit design, and it can outperform other generalist schemes in the literature in sequence size and device count. Moreover, its implementation flexibility simplifies the handling of functions with varying fan-ins.

An incompletely specified Boolean function, also known as a Boolean relation, can be described by any combination of its on-set, off-set, and don't care (DC) set pairs. To transform a Boolean relation into a Boolean function (fully specified), we have to assign the DCs from the original specification. Depending on the DCs assignment, a better function minimization may result from the original specification. This article presents a method for joining two BDDs by describing the on-set and off-set of an incompletely specified$f$function into a single BDD for a fully specified coverage of the function. The proposed method is compared with the Restrict, Constrain and LICompaction methods implemented by the CUDD package, which are references for this problem using BDDs. In addition to these methods, we also compare our results with the Join method, which is a more recent proposal for the problem of assigning and minimizing incompletely specified Boolean functions. The LI-Compaction method presented the largest number of BDD nodes among the analyzed methods. Compared to the LICompaction method, the Restrict method produced 2.12% fewer nodes, the Constrain and Join methods produced 1.95% fewer nodes, while our method produced 24.80% fewer nodes.

The technology scaling has boosted the importance and gravity of radiation faults. Hardening techniques are required to ensure a high level of reliability, mainly to the harsh critical applications. Hardware redundancy remains the most adopted option to deal with fault tolerance, mostly the TMR technique. However, the weakness of this technique is the voter circuit. This paper investigates the robustness of nineteen majority voter designs in the presence of a SET. The analysis explores critical diffusion areas and LET threshold. The results show designs with 3X difference in the number of critical diffusion areas and 6X in the LET threshold.

The aggressive technology scaling has significantly affected the circuit reliability. Several techniques have been explored to mitigate the scaling effects and guarantee a satisfactory reliability level. In this context, estimating circuit reliability is crucial and a challenge that has not yet been overcome. For decades, traditional reliability estimation techniques have used fixed logic gates reliability values. Recently, methods demonstrate that using fixed gate reliability values compromises the accuracy of the analysis. This work evaluates the impact of the estimated logic gate susceptibility in the reliability of several benchmarks circuits mapped with different sets of logic gates. The obtained results show a discrepancy in the reliability of the same circuit. However, the change in the reliability behavior may be considered the main contribution of this work. The utilization of fixed reliability values for logic gates provides reliability values inversely proportional to the number of gates in the circuit. The used approach captures the logical characteristics of the gates. The same circuit mapped with basic gates presents a difference in MTBF of 20%, while the one mapped with a complex set of gates is bigger than 70%.

Approximate computing is an attractive paradigm for reducing the design complexity of error-resilient systems, therefore, improving performance and saving power consumption. In this work, we propose a new two-level approximate logic synthesis method based on cube insertion and removal procedures. The experimental results have shown significant literal count and runtime reduction compared to the state-of-the-art approach. The method scalability is illustrated for a high error threshold over large benchmark circuits. The obtained solutions have presented a literal number reduction up to 38%, 56%, and 93% with respect to an error rate of 1%, 3%, and 5%, respectively.

Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning.

The OpenROAD project is an ambitious initiative seeking to develop an automated, open-source RTL-to-GDSII flow. To build its complex toolset, OpenROAD brings together a team of industry experts, veteran scholars, and enthusiastic students from different schools and different countries. This paper first presents our path to becoming OpenROAD contributors, highlighting the nature of the OpenROAD project, the recruitment process, and the necessary logistics. We then summarize the contributions of the Brazilian team to the OpenROAD project; these comprise the development of five tools and more than 10K lines of released code, along with authorship or co-authorship of two publications in the research literature. We also summarize our experiences from working in a large software project: (i) working environment and relationship with people from around the world; (ii) task management and short turnaround times; (iii) continuous integration and testing; etc. Finally, we highlight the challenges of "refurbishing" academic research codes for use in the design of production ICs.

New design methodologies are needed to improve the circuit robustness to deal with technology scaling issues. Traditional fault-tolerant approaches present severe overheads. Alternative solutions based on partial fault tolerance and fault avoidance are considered a possible solution to the reliability problem. An accurate evaluation of circuit reliability is fundamental to allow a reliability-aware automated design flow, where the synthesis tool could rapidly cycle through several circuit configurations to assess the best option. Most of the circuit reliability estimation methods use logic gate information as the starting point. The difference in logic gates reliability is neglected. This work proposes models capable of analyzing logic gates susceptibility in different abstraction levels. Three methods are proposed based on transistor arrangement, stick diagram, and layout of the logic gates. A 45nm standard cell library is used to validate the proposed methods. The achieved results are used to analyze ISCAS'85 benchmark circuit reliability. The obtained Mean Time Between Failures (MTBF) shows a considerable reduction of almost 50% compared to the values from traditional fixed logic gate reliability.

The progressive downscaling of feature sizes increases the susceptibility to Single Event Effects in integrated circuits. As a manner to mitigate soft errors, solutions incur significant performance and area penalties, especially when a design with fault-tolerant structure is overprotected. Probabilistic methods such as Probabilistic Transfer Matrix and Signal Probability Reliability Multi-Pass are prone to multiple faults scenario to evaluate circuits reliability. However, it is necessary that the probabilistic matrices of the gates being accurate enough for this task. This paper proposes a method to evaluate gate failure rate considering faults in Layout-Level. This method can be used to enrich the probabilistic matrices creation taking into account the characteristics of the layout in order to evaluate gate reliability and the failure rate more precisely. Results show a reduction of 40% in the failure rate just choosing the best layout alternative for the same logic function.

The circuit reliability in nanometer technologies has become an important aspect of circuit design. Techniques to improve reliability usually increase project costs. To avoid overdesign, techniques to estimate circuit reliability are commonly used. These techniques usually explore probabilistic Matrices to compute the circuit reliability. The matrices used to represent logic functions are simplified do not taking into account the logic gate design. In this way, the main goal of this thesis is to propose a method capable of creating probabilistic matrices from logic gates layouts and then improve the accuracy of the reliability evaluation methods.

In this work, we present a flow for the Incremental Timing-Driven Placement problem. Given a legal placement, the aim is to reduce the circuit's timing violations without changing significantly the cell density, subject to a maximum displacement constraint. Our flow consists of two core steps: useful clock skew optimization and critical path fine tuning. During useful clock skew optimization, sequential cells are replaced, seeking to minimize clock skew. After that, a quadratic formulation is used to further reduce critical path delays. An incremental legalization tool is also presented, which supports the methods developed in this work. Our Incremental Timing-Driven Placement flow can achieve, on average, 0.3%, 26.2%, 8.7% and 23.7% of the normalized quality score improvement compared to state-of-the-art algorithms.

Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary according the fabric pattern optimization possibilities. Yield improvements have to be traded-off against area and performance losses due to regular design rules. This paper evaluates the losses introduced by using regular fabrics. Several benchmark circuits have been mapped over different regular layout templates through specific cell libraries built for this purpose. Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template.

We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown Weibull distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32 × 32 test array implemented in a 130-nm bulk CMOS process. Results show that this system is capable of taking accurate measurements across a range of voltages and temperatures, which is critical for extrapolating accelerated stress experiment results to expected device lifetimes under realistic operating conditions.

This paper proposes a new method to estimate static power dissipation in digital circuits by evaluating simultaneously subthreshold and gate oxide leakage currents. The estimation method is performed over logic cells, including CMOS complex gates with multi-level series-parallel devices. Experimental results have been carried out on different fabrications processes, and good correlation with HSPICE simulator was obtained at cell and circuit levels. The algorithm presents a speed up of 80x when compared to HSPICE.

This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis. Both contributions present significant influence in the logic circuit leakage prediction when CMOS complex gates are extensively used. The proposed leakage model has been validated through electrical simulations, taking into account a 130nm CMOS technology, with good correlation of the results.