Substrate noise problems in a system-on-a-chip hamper the smooth cohabitation between analog and digital circuitries on the same die. Solving those problems will shorten the time to market. This paper presents a methodology that gives designers the necessary insight to solve this substrate noise problem. The methodology combines the strengths of the electromagnetic simulator, the parasitic extractor, and the circuit simulator. Its main assets are the ease of use, an acceptable simulation time, and a good accuracy. Moreover, this methodology does not need doping profiles that are hard to get hold off. The proposed methodology is demonstrated on two challenging examples: a 48-53-GHz LC voltage-controlled oscillator and a dc-to-5-GHz wideband receiver designed, respectively, in a 0.13-mum and a 90-nm CMOS technology. The substrate noise coupling mechanisms are revealed for both examples in a simulation time of less than 2 hours. The methodology is successfully validated by measurements performed on real-life prototypes of those examples with an accuracy of 1-2 dB.

Analyzing the stability of an analog circuit is an important part of the circuit design. Several commercial simulators are equipped with special stability analysis techniques. Problems arise when your design kit does not support such simulator. Another issue is when the designer wants to get insight into the sources of the instability to propose a stabilization. This can be done through analyzing the open-loop or the closed-loop transfer function of the circuit. The aim of this paper is to propose an automated analysis method which identifies the nodes to be considered for stabilization. The method does not need to break feedback loops or to manipulate netlists. It only uses AC simulations and does not require the full modified nodal equations. The method is illustrated on 3 design examples: a voltage controlled oscillator (VCO), a reference bias circuit and the common-mode feedback network in a gm-C filter