As the descendant ofspin-transfer random access memory(STT-RAM), racetrack memory technology saves data in magnetic domains along nanoscopic wires. Such a unique structure can achieve unprecedentedly high storage density meanwhile inheriting the promising features of STT-RAM, such as fast access speed, non-volatility, zero standby power, hardness to soft errors, and compatibility with CMOS technology. Moreover, the recent success in planar racetrack nanowire promised its fabrication feasibility and continuous scalability. In this paper, we investigate the design and optimization of racetrack memory as last-level cache by embracing design considerations across multiple abstraction layers, including the cell design, the array structure, the architecture organization, and the data management. The cross-layer optimization makes racetrack memory based last-level cache achieve 6.4$\times$reduction in area, 25 percent enhancement in system performance, and 62 percent saving in energy consumption, compared to STT-RAM cache design. Its benefit over SRAM technology is even more significant.

Spin-torque transfer RAM (STT-RAM), a promising alternative to static RAM (SRAM) for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. However, physical effects of technology scaling down to 45 nm and below, in particular, process variation, introduce the previously unreported and alarming trends in read performance and reliability due to reduced sensing margins and increasing error rates. In this brief, we study the scaling trends of STT-RAM from 65 down to 22 nm as they pertain to read performance, including a 50% increase in sensing versus peripheral circuit delay ratio and a more than 80% increase in uncorrectable read error rates. Through differential sensing, we show how 22 nm can return to sense delay ratio levels at 65 nm and uncorrectable read errors can be reduced by an order of magnitude. Through a case study of a multilevel STT-RAM cache, we show how a reconfigurable cache cell can create an extreme access mode (X-mode) based on differential sensing improve to outperform the state-of-the-art STT-RAM caching techniques in both raw performance and performance per watt by more than 10% while still reducing energy consumption over SRAM caches by more than 1/3.

STT-RAM is an emerging NVRAM technology that promises high density, low energy and a comparable access speed to conventional SRAM. This paper proposes a hybrid L1 cache architecture that incorporates both SRAM and STT-RAM. The key novelty of the proposal is the exploition of the MESI cache coherence protocol to perform dynamic block reallocation between different cache partitions. Compared to the pure SRAM-based design, our hybrid scheme achieves 38% of energy saving with a mere 0.8% IPC degradation while extending the lifespan of STT-RAM partition at the same time.

The recent successful integration of magnetic racetrack memory forecasts a new computing era with unprecedentedly high-density on-chip storage. However, racetrack memory accesses require frequent magnetic domain shifting, introducing overheads in access latency and energy consumption. In this paper, we evaluate and compare several different physical layout strategies and array organizations. From this evaluation, a workload-oriented racetrack LLC architecture is proposed that combines different array types, each of which is tailored to a specific data access pattern. Further, a resizable cache access strategy is applied to reduce shifting overheads at runtime. Our simulation results show that compared with the leading racetrack-based cache, the proposed racetrack LLC can improve system performance by 13.2% reduce LLC energy consumption by 30.4%.

Spin-transfer torque random access memory (STT-RAM) is the most promising candidate to be universal memory due to its good scalability, zero standby power, and radiation hardness. Having a cell area only 1/9 to 1/3 that of SRAM, allows for a much larger cache with the same die footprint. Such reduction of cell size can significantly shrink the cache array size, leading to significant improvement of overall system performance and power consumption, especially in this multicore era where locality is crucial. However, deploying STT-RAM technology in L1 caches is challenging because write operations on STT-RAM are slow and power-consuming. In this paper, we propose a range of cache hierarchy designs implemented entirely using STT-RAM that deliver optimal power saving and performance. In particular, our designs use STT-RAM cells with various data retention times and write performances, made possible by novel magnetic tunneling junction designs. For L1 caches where speed is of utmost importance, we propose a scheme that uses fast STT-RAM cells with reduced data retention time coupled with a dynamic refresh scheme. In the dynamic refresh scheme, another emerging technology, memristor, is used as the counter to monitor the data retention of the low-retention STT-RAM, achieving a higher array area efficiency than an SRAM-based counter. For lower level caches with relatively larger cache capacities, we propose a design that has partitions of different retention characteristics, and a data migration scheme that moves data between these partitions. The experiments show that on the average, our proposed multiretention level STT-RAM cache reduces total energy by as much as 30%-74.2% compared to previous single retention level STT-RAM caches, while improving instruction per cycle performance for both two-level and three-level cache hierarchies.

The racetrack memory technology utilizes magnetic domains along a nanoscopic wire to obtain ultra-high data storage density. The recent success in the planar racetrack nanowire promised its fabrication feasibility and future scalability, bringing more design challenges and opportunities. In this paper, we initialize the optimization of racetrack memory embracing design considerations across multiple layers, including cell design, array structure, architecture organization, and data management. Our evaluation shows that racetrack memory based cache can achieve 6.4x area reduction, 25% performance enhancement, and 62% energy saving, compared to STT-RAM cache design. The benefit over SRAM technology is even more significant.

Using the spin-transfer torque random access memory (STT-RAM) technology as lower level on-chip caches has been proposed to minimize leakage power consumption and enhance cache capacity at the scaled technologies. However, programming STT-RAM is a stochastic process due to the random thermal fluctuations. Conventional worst-case (corner) design with a fixed write pulse period cannot completely eliminate the write failures but maintain it at a low level by paying high cost in hardware complexity and system performance. In this work, we systematically study the impacts of the stochastic switching of STT-RAM on circuit and cache performance. Two probabilistic design techniques, write-verify-rewrite with adaptive period (WRAP) and verify-one-while-writing (VOW), then are proposed for performance improvement and write failure reduction. Our simulation results show that compared to the result of the conventional design using Hamming Code to correct the write failures, WRAP is write error free while reducing the cache write latency and energy consumption by 40% and 26%, respectively. When an extremely low write failure rate (i.e., 10−22) is allowed, VOW can further boost the reductions on write latency and energy to 52% and 29%, respectively. Furthermore, a hybrid STT-RAM based cache hierarchy taking advantages of probabilistic design techniques is proposed. The novel hierarchy can reduce the write failure rate of STT-RAM cache to 10−30, while improving the speed by 6.8% and saving 15% of energy consumption compared to a conventional design with Hamming Code.

The spin-transfer torque random access memory (STT-RAM) has gained increasing attentions for its high density, fast read access, zero standby power, and good scalability. The recently proposed retention-relax design further improves STT-RAM write access performance and makes it even more promising as an on-chip memory technology. Nevertheless, the process variations could affect the writability of STT-RAM cells. The situation for retention-relax design is even more severe. In this paper, we comprehensively study the impact of process variations, including those from both CMOS and magnetic technologies, on key STT-RAM design parameters. Furthermore, we propose process variation aware nonuniform cache access (PVA-NUCA) technique for large STT-RAM cache design. Besides the varying interconnect latencies determined by memory locations, PVA-NUCA compensates write time variations of STT-RAM cells resulted by process variations. Two algorithms, namely, conservative promotion and aggressive prediction, have been introduced and evaluated. A conflict-reduction mechanism is utilized to degrade the data access miss rate caused by conflicts of access-intensive data blocks. Compared to the traditional STT-RAM dynamic nonuniform cache access (DNUCA), our proposed dynamic PVA-NUCA can improve 25.29% of IPC performance and reduce 26.4% of STT-RAM cache energy consumption, with < 1% of area overhead.

In the past, the spin-transfer torque RAM (STT-RAM) suffered from the slow write speed and the high write energy consumption. The latest progress in device engineering has dramatically reduced the write time to a few nanoseconds and hence enabled the fast-switching STT-RAM (FS-STT-RAM). However, the enhancement in write performance results in the degradation of read operations, in terms of both speed and data reliability. Our analysis shows that the read performance becomes critical. Based upon the tradeoff among the read latency, read errors, and system performance, we propose a new FS-STT-RAM architecture, which can switch between two operation modes for either high data accuracy or low power consumption with the support of operation system. In the high accuracy mode, FS-STT-RAM applies the rewrite-after-read scheme to eliminate the data disturbances induced by read current. Even so, with enhancement from shadow rewrite buffer and bit invert scheme, it gains an average 19% improvement in energy-delay-product (EDP) compared to a conventional STT-RAM. When an application can afford a very low chance of read disturbance, the proposed FS-STT-RAM can operate in the low power mode and further boost the average EDP improvement to 34%.

In this article, we propose a data storage system with the emerging nonvolatile memory technologies used for the implantable electrocardiography (ECG) recorder. The proposed storage system can record the digitalized real-time ECG waveforms continuously inside the implantable device and export the stored data to external reader periodically to obtain a long-term backup. Spin transfer torque random access memory (STT-RAM) and spintronic memristor are selected as the storage elements for their nonvolatility, high density, high reliability, low power consumption, good scalability, and CMOS technology compatibility. The new read and write schemes of STT-RAM and spintronic memristors are presented and optimized to fit the specific application scenario. The tradeoffs among data accuracy, chip area, and read/write energy for the different technologies are thoroughly analyzed and compared. Our simulation results show the configuration with a data sampling rate (e.g., 128 Hz) and a quantization resolution (e.g., 12 bits) can record 18-hour real-time data within ~ 3.6-mm 2 chip area when the data storage is built with single-level cell (SLC) STT-RAMs. Daily energy consumption is 5.46 mJ. Utilizing the multilevel cell (MLC) STT-RAMs or the spintronic memristors as the storage elements can further reduce the chip area and decrease energy dissipation.

Spin-transfer torque random access memory (STT-RAM) has demonstrated great potentials as a universal memory for its fast access speed, zero standby power, excellent scalability, and simplicity of cell structure. However, large process variations of both magnetic tunneling junction (MTJ) and CMOS process severely limit the yield of STT-RAM chips and prevent the massive production from happening. In this paper, we analyze and compare the impacts of process variations on various sensing schemes of STT-RAM design. On top of it, we propose a novel voltage-driven nondestructive self-reference sensing scheme to enhance the STT-RAM chip yield by significantly improving sense margin. Monte Carlo simulations of a 16-Kb STT-RAM array shows that our proposed scheme can achieve the same yield as the previous nondestructive self-reference sensing scheme while improving the sense margin by five times with the similar access performance and power.

Spin-transfer torque random access memory (STT-RAM) has received increasing attention because of its attractive features: good scalability, zero standby power, non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1/9 ~ 1/3 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system performance through reducing cache misses. However, deploying STT-RAM technology in L1 caches is challenging because of the long and power-consuming write operations. In this paper, we propose both L1 and lower level cache designs that use STT-RAM. In particular, our designs use STT-RAM cells with various data retention time and write performances, made possible by different magnetic tunneling junction (MTJ) designs. For the fast STT-RAM bits with reduced data retention time, a counter controlled dynamic refresh scheme is proposed to maintain the data validity. Our dynamic scheme saves more than 80% refresh energy compared to the simple refresh scheme proposed in previous works. A L1 cache built with ultra low retention STT-RAM coupled with our proposed dynamic refresh scheme can achieve 9.2% in performance improvement, and saves up to 30% of the total energy when compared to one that uses traditional SRAM. For lower level caches with relative large cache capacity, we propose a data migration scheme that moves data between portions of the cache with different retention characteristics so as to maximize the performance and power benefits. Our experiments show that on the average, our proposed multi retention level STT-RAM cache reduces 30 ~ 70% of the total energy compared to previous works, while improving IPC performance for both 2-level and 3-level cache hierarchy.

Spin-Transfer Torque Random Access Memory (STT-RAM) demonstrated great potentials as an universal memory for its fast access speed, zero standby power, excellent scalability and simplicity of cell structure. However, large process variations of both magnetic tunneling junction and CMOS process severely limit the yield of STT-RAM chips and prevent the massive production from happening. In this paper, we analyze the impacts of process variations on various sensing schemes of STT-RAM. Based on our analysis, we propose a novel voltage-driven non-destructive self-reference sensing scheme (VDRS) to enhance the STT-RAM chip yield by significantly improving sense margin. Monte-Carlo simulations of a 16Kb STT-RAM array shows that VDRS can achieve the same yield as the previous non-destructive self-reference sensing scheme while improving the sense margin by 5.16 times with the similar access performance and power.