Shin-De Lee

dblp:93/615 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2001
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 50% Electronic design automation · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.012001
Charge-sharing alleviation and detection for CMOS domino circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Integrated circuit design › digital circuit design › dynamic logic
domino logic
0.012001
Charge-sharing alleviation and detection for CMOS domino circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Electronic design automation › hardware verification and test
fault testing
0.012001
Charge-sharing alleviation and detection for CMOS domino circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001
Electronic design automation › hardware verification and test
hardware verification
0.012001
Charge-sharing alleviation and detection for CMOS domino circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2001

Methods — techniques the papers use, named apart from their topics

transistor reordering · 0.0test vector generation · 0.0
YearPublicationVenuePosition
2001 Charge-sharing alleviation and detection for CMOS domino circuits
abstract
Charge sharing, which occurs in any complementary metal-oxide-semiconductor (CMOS) domino gate, may degrade the output voltage level or may even cause an erroneous output value. In this paper, this problem is thoroughly investigated by considering circuit topology and circuit function. We describe a method to measure the sensitivity [called charge-sharing (CS) vulnerability] of the CS problem for each domino gate. A method to derive the CS vulnerability and the test vector for each domino gate is suggested. We also propose a transistor reordering method to dramatically reduce the CS vulnerabilities for all domino gates so that the CS problem can be alleviated. We also prove theoretically that a set of test vectors generated for single charge-sharing faults (SCSFs) can also detect all multiple charge-sharing faults (MCSFs). This good property significantly guarantees the test quality for the CS faults of domino circuits.
Shih-Chieh Chang 0001, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4