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Arun N. Lokanathan

dblp:93/6644 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 100%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
design optimization
0.131999
A methodology for concurrent process-circuit optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999
Process Multi-Circuit Optimization · DAC 1998
A Methodology for Concurrent Fabrication Process/Cell Library Optimization · DAC 1996
Electronic design automation
multi-objective optimization
0.011999
A methodology for concurrent process-circuit optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999
Electronic design automation › logic synthesis
circuit optimization
0.011998
Process Multi-Circuit Optimization · DAC 1998
Electronic design automation › design optimization
standard cell library optimization
0.011996
A Methodology for Concurrent Fabrication Process/Cell Library Optimization · DAC 1996
Electronic design automation › design for manufacturability › design for yield
yield enhancement
0.021999
A methodology for concurrent process-circuit optimization · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999
A Methodology for Concurrent Fabrication Process/Cell Library Optimization · DAC 1996

Methods — techniques the papers use, named apart from their topics

concurrent subspace optimization · 0.0object-oriented design · 0.0multi-objective optimization · 0.0
YearPublicationVenuePosition
1999 A methodology for concurrent process-circuit optimization
abstract
In order to optimize integrated circuit designs, it is critical not only for circuit designers to adjust circuit geometries but also for process developers to adjust device characteristics for optimal overall system performance. This paper describes concurrent process-circuit optimization (CPCO), a methodology for concurrent integrated circuit optimization that spans the fabrication process design and circuit design disciplines. CPCO enables process developers and circuit designers to work coordinately toward the common goal of optimizing a system-level objective, and therefore produces better designs than single-discipline optimization schemes. The methodology logically partitions the overall integrated circuit optimization task into loosely coupled process and circuit design tasks that may proceed concurrently-this produces substantial time savings over a flat "all-at-once" optimization approach. Finally, the CPCO method formulates a multiobjective optimization problem that may be used to negotiate tradeoffs in adjusting a single process to optimize multiple circuits, to optimize nominal circuit performances or to improve circuit yield. The implementation of the CPCO method in an extensible object-oriented software architecture is described. Results of applying the methodology to integrated circuit design examples with industrial grade simulation tools are presented. The results demonstrate substantial performance gains over separate process/circuit optimization and substantial time savings over "all-at-once" combined optimization.
Arun N. Lokanathan, Jay B. Brockman
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1998 Process Multi-Circuit Optimization
abstract
This paper describes the implementation of a concurrent methodology for integrated circuit optimization that spans the fabrication process design and circuit design disciplines. Results from this methodology show substantial performance gains as compared to a separate process/circuit optimization and a substantial time savings over an “all-at-once” combined optimization.
Arun N. Lokanathan, Jay B. Brockman
DAC1
1996 A Methodology for Concurrent Fabrication Process/Cell Library Optimization
abstract
This paper presents a methodology for concurrently optimizing an IC fabrication process and a standard cell library in order to maximize overall yield.The approach uses the Concurrent Subspace Optimization (CSSO) algorithm, which has been developed for general coupled, multidisciplinary optimization problems.An example is provided showing the application of the algorithm to optimizing a mixed analog-digital library on a CMOS process.
Arun N. Lokanathan, Jay B. Brockman, John E. Renaud
DAC1