In this paper, we present an algorithm of transistor placement that takes unroutable standard cells and makes them routable by moving transistors in local windows. It converts the task of placement of gridded FinFETs into a Boolean problem and employs SAT, an accurate computing technology. The Boolean problem models possible moves of transistors as well as possible routes. Track assignment mimics an industrial router. Manufacturing rules are modeled using a special layout data model that is directly translated into SAT. A SAT solver finds legal transistor placement ensuring subsequent DRC-clean routing. The speed of SAT solvers makes the flow practical for most complex cells from a standard cell library.

In this paper, we propose a routing flow for nets within a standard cell that generates layout of standard cells without any design rule violations. Design rules, density rules for metal fill, and pin-access requirements are modeled via Boolean formulas for discrete layout objects on grids. Formulas are translated into a single Boolean satisfiability problem (SAT). Having constraints on net connectivity and candidate routes, the SAT solver produces legal and complete routing concurrently for all nets satisfying mandatory pin-access and density requirements. A SAT-based optimization engine minimizes undesired layout patterns such as DFM (design-for-manufacturing) hot spots.

We propose a flow for routing nets within a standard cell that 1) generates candidate routes for point-to-point segments; 2) finds conflicts (electrical shorts and geometric design rule violations) between candidate routes; and 3) solves a SAT instance producing a legal and complete routing for all nets in the standard cell. This approach enables routing automation for cutting-edge process technology nodes. We present how to make this technique more effective by introducing pruning techniques to reduce the work required in all three steps. We also show how we can further optimize routing quality within the SAT formulation through the use of successively more stringent constraints. Recent improvements in the speed of SAT solvers make such a formulation practical for even complex standard cells. A routing tool based on our SAT formulation is currently being used to route real industrial standard cell layouts. It demonstrates acceptable runtime and 89% coverage of our industrial standard cell library, including scan flip-flops, adders, and multiplexers. We also observe a significant reduction in amount of metal2 routing in comparison with industrial hand-crafted standard cells.

In this work we propose a regular layout fabric practical for industrial random logic design and present cell synthesis algorithms specialized to this fabric. We show results on an industrial test-case where physical synthesis onto a library of extremely regular cells results in only 7% increase in leakage in comparison to traditional standard cells. We also show that using this fabric based cell synthesis system allows better overall area by allowing more upper layer routing. We achieve a 4% routable die size reduction by simultaneous cell synthesis and custom M1 routing.

We present a repeater insertion flow targeted for circuit-level repeater insertion at different stages of physical synthesis. We propose how to organize circuit-level flow around the net-based dynamic programming algorithm for repeater insertion. We discuss what accuracy is required for the timing model at different stages of our flow and what stages determine the quality of the overall results. Our flow was tested on industrial designs with very high-fanout nets. It is capable of simultaneously solving the problem of fanout optimization and repeater insertion during the physical synthesis. We have achieved more than 60% reduction in repeater area without compromising timing by considering sink polarity during the topology generation and applying a set of refinement techniques.