This paper presents a novel flip-flop clustering and relocation framework to help reduce the overall chip power consumption. Given an initial legalized placement, our goal is to reduce the wirelength of the clock network by reducing distance between flip-flops and their drivers, while minimize the disturbance of original placement result. The idea is to form flip-flops into clusters, such that all flip-flops within each cluster can be placed near a single clock buffer and connected by a simple routing structure. Therefore, overall clock network wirelength can be greatly reduced and significant power savings can be achieved. In particular, we propose a modified K-means algorithm which effectively assigns flops into clusters at the clustering step. Then, at the relocation step, flops are actually relocated and regularly structured clusters are formed. Our framework is evaluated on real industrial benchmarks. We compare our framework with a flow without flop clustering and an industrial window based flop clustering flow. Experimental results show our framework can achieve significant dynamic power savings while has less disturbance of the original placement.

We present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing in this paper. Both wire widths and buffer sizes are chosen from user-defined discrete sets. Our algorithm integrates the quadratic programming approach for handling a wire branch into the dynamic programming (DP) framework. Our experimental results show that our hybrid dynamic/quadratic programming algorithm is faster, more accurate, and uses considerably less memory than the pure DP approach.

We present an algorithm for delay minimization of intercon- nect trees by simultaneous buffer insertion/sizing and wire sizing in this paper. Both wire widths and buffer sizes are chosen from user-defined dis- crete sets. Our algorithm integrates the quadratic programming approach for handling a wire branch into the dynamic programming (DP) frame- work. Our experimental results show that our hybrid dynamic/quadratic programming algorithm is faster, more accurate, and uses considerably less memory than the pure DP approach.