Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging process provides one method to reduce large design margins that are otherwise required to offset circuit aging. This work extends previous research by contributing a sensing scheme that employs on-chip sensors capable of accurately tracking NBTI pMOS current degradations across process, temperature, and varying activity factors. Results show that a 7600$\mu{\hbox {m}}^{2}$sensing area achieves an overall system accuracy of 90% at a voltage threshold precision of 2 mV. We thoroughly describe the sensor design and the underlying statistics used to determine overall accuracy and precision. Furthermore, a novel sensor distribution method is presented that uses an existing scan-chain methodology to mask the overhead of adding the on-chip sensors.

NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks both NBTI and PBTI for both logic and SRAM circuits. Embedded in an SRAM array the sensor takes the form of a 6T SRAM cell and is at least 30x smaller than previous designs. Extensively reusing the SRAM peripheral circuitry minimizes control logic overhead. Sensing overhead is further amortized as the sensors can be both reconfigured and recycled as functional SRAM cells, potentially increasing SRAM yield when other bit cells fail due to initial process variation or long time aging effects. The paper also proposes a variation-aware sensor system design methodology by quantifying and leveraging the tradeoff between the size and number of sensors and the system sensing precision. Design examples show that a system of 500 sensors can achieve 4mV precision with 98.8% confidence, and a system of 1K sensors designed for 1M SRAM bit cells achieves 2000x area overhead reduction compared to a worst-case based approach.

This paper describes a 130 nm CMOS sub-threshold (sub-VT) mixed-signal system-on-chip (SoC) that acquires and processes an electrocardiogram (ECG) signal for wireless ECG monitoring. Low power ECG devices permit continuous monitoring for longer durations between power recharging. Co-designing the digital and analog blocks creates opportunities for reducing power at the system level. The SoC uses a sub-threshold digital microcontroller (μC) for adaptive control of the sub-VT biased analog components and for processing the ECG data. The μC operates from 0.24 V to 1.2 V and consumes as little as 1.51 pJ per instruction. The SoC consumes only 2.6 μW while providing raw ECG data or processed heart rate data, which can lower the wireless data rate by 500X.